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參數(shù)資料
| 型號(hào)： | MC68HC11EA9VFN3 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 28/58頁 |
| 文件大?。?/td> | 583K |
| 代理商： | MC68HC11EA9VFN3 |
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MOTOROLA
MC68HC11EA9
34
MC68HC11EA9TS/D
MCS — Module Clock Select
This bit determines which clock signal drives the SCI and timer.
0 = EXTAL is the clock source for SCI and timer divider chains
1 = 4XCLK is the clock source for the SCI and timer divider chains
LCK— Synthesizer Lock Detect Flag
This is a read-only status bit that indicates when the PLL has stabilized. BCS cannot be set (selecting
VCOUT as a clock source) until LCK is set.
0 = The PLL is not stable
1 = The PLL has stabilized
WEN — WAIT Enable
This bit determines whether the EXTAL signal will be used to drive the CPU clocks while the device is
in WAIT mode. When this feature is enabled, entering wait mode clears BCS (selecting EXTAL as the
source for CPU clocks) and reduces the PLL frequency to the lowest value, modulus 1. Any interrupt or
reset or the assertion of the RAF bit within the SCI (if the receiver is enabled by RE = 1) will allow the
PLL to resume operation at the frequency selected in SYNR register. Then the user must set BCS to
select VCOUT as the source for CPU clocks.
0 = VCOUT remains connected to the 4XCLK circuit during operation in WAIT mode.
1 = After stacking prior to entering WAIT mode, BCS is cleared and the PLL is maintained at the
lowest frequency available (modulus 1).
This register resets to $06 for a preset multiplication factor of 14.
SYNX[1:0] — Binary Tap Select Bits
These two bits select one of four binary taps. SYNX[1:0] affect the frequency multiplication factor, vari-
able
X according to the formula below.
SYNY[5:0] — Modulo Counter Rate Select Bits
These six bits select one of 64 binary values that affect the frequency multiplication factor, variable
Y
according to the formula below.
Where
X = the value represented by bits SYNX[1:0]
Y = the value represented by bits SYNY[5:0]
7.2 Main Timer
The main timer consists of the timer prescaler, the free-running counter, and the capture/compare unit.
The timer prescaler selects one of four division rates and drives the free-running 16-bit counter. The
capture/compare unit has three channels for input capture, four channels for output compare, and one
channel that can be configured as a fourth input capture or a fifth output compare. Timer channels con-
figured for input capture (ICx) cause the current value of the free-running counter to be latched into an
input capture register (TICx) when a pulse edge is detected on the corresponding pin. Channels con-
figured for output compare allow a pulse to be output when the free-running counter matches a value
loaded into an output compare register (TOCx). Figure 9 shows a detailed block diagram of the timer
prescaler and the capture/compare unit.
SYNR — Frequency Synthesizer Control
$1037
BIT 7
654321
BIT 0
SYNX1
SYNX0
SYNY5
SYNY4
SYNY3
SYNY2
SYNY1
SYNY0
RESET:
00000110
2Y
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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