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| 型號(hào)： | MC68HC11EA9VFN3 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁(yè)數(shù)： | 31/58頁(yè) |
| 文件大?。?/td> | 583K |
| 代理商： | MC68HC11EA9VFN3 |
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MC68HC11EA9
MOTOROLA
MC68HC11EA9TS/D
37
All TOCx register pairs reset to $FFFF.
This is a shared register and is either input capture 4 or output compare 5 depending on the state of bit
I4/O5 in PACTL. Writes to TI4/O5 have no effect when this register is configured as input capture 4. The
TI4/O5 register pair resets to $FFFF.
TOC1–TOC4 — Timer Output Compare
$1016–$101D
$1016
BIT 15
14
13
12
11
10
9
BIT 8
TOC1 (HI)
$1017
BIT 7
654321
BIT 0
TOC1 (LO)
$1018
BIT 15
14
13
12
11
10
9
BIT 8
TOC2 (HI)
$1019
BIT 7
654321
BIT 0
TOC2 (LO)
$101A
BIT 15
14
13
12
11
10
9
BIT 8
TOC3 (HI)
$101B
BIT 7
654321
BIT 0
TOC3 (LO)
$101C
BIT 15
14
13
12
11
10
9
BIT 8
TOC4 (HI)
$101D
BIT 7
654321
BIT 0
TOC4 (LO)
TI4/O5 — Timer Input Capture 4/Output Compare 5
$101E–$101F
BIT 15
14
13
12
11
10
9
BIT 8
TCNT (HI)
BIT 7
654321
BIT 0
TCNT (LO)
TCTL1 — Timer Control 1
$1020
BIT 7
654321
BIT 0
OM2
OL2
OM3
OL3
OM4
OL4
OM5
OL5
RESET:
00000000
Table 14 Output Compare Channel Configuration
OMx
OLx
Action on Successful Compare
0
None — Output Compare Channel (OCx) disabled
0
1
Toggle OCx output pin logic level
1
0
Drive OCx output pin low
1
Drive OCx output pin high
TCTL2 — Timer Control 2
$1021
BIT 7
654321
BIT 0
EDG4B
EDG4A
EDG1B
EDG1A
EDG2B
EDG2A
EDG3B
EDG3A
RESET:
00000000
Table 15 Input Capture Channel Configuration
EDGxB
EDGxA
Input Capture Configuration
0
Input Capture Channel (ICx) disabled
0
1
Capture on rising edge on ICx input pin
1
0
Capture on falling edge on ICx input pin
1
Capture on any edge on ICx input pin
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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