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Timer Interface Module (TIM)
Functional Description
MC68HC(7)08LN56 — Rev. 2.0
General Release Specication
MOTOROLA
Timer Interface Module (TIM)
143
NONDISCLOSURE
AGREEMENT
REQUIRED
Setting the MS2B bit in TIM channel 2 status and control register (TSC2)
links channel 2 and channel 3. The output compare value in the TIM
channel 2 registers initially controls the output on the PTE2/TCH2 pin.
Writing to the TIM channel 3 registers enables the TIM channel 3
registers to synchronously control the output after the TIM overflows. At
each subsequent overflow, the TIM channel registers (2 or 3) that control
the output are the ones written to last. TSC2 controls and monitors the
buffered output compare function, and TIM channel 3 status and control
register (TSC3) is unused. While the MS2B bit is set, the channel 3 pin,
PTE3/TCH3, is available as a general-purpose I/O pin.
NOTE:
In buffered output compare operation, do not write new output compare
values to the currently active channel registers. Writing to the active
channel registers is the same as generating unbuffered output
compares.
10.4.6 Pulse Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare
channel, the TIM can generate a PWM signal. The value in the TIM
counter modulo registers determines the period of the PWM signal. The
channel pin toggles when the counter reaches the value in the TIM
counter modulo registers. The time between overflows is the period of
the PWM signal.
As Figure 10-2 shows, the output compare value in the TIM channel
registers determines the pulse width of the PWM signal. The time
between overflow and output compare is the pulse width. Program the
TIM to clear the channel pin on output compare if the state of the PWM
pulse is logic one. Program the TIM to set the pin if the state of the PWM
pulse is logic zero.
The value in the TIM counter modulo registers and the selected
prescaler output determines the frequency of the PWM output. The
frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIM counter modulo registers produces a PWM
period of 256 times the internal bus clock period if the prescaler select