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Serial Communications Interface Module (SCI)
Functional Description
MC68HC(7)08LN56 — Rev. 2.0
General Release Specication
MOTOROLA
Serial Communications Interface Module (SCI)
207
NONDISCLOSURE
AGREEMENT
REQUIRED
12.5.2.1 Character Length
The transmitter can accommodate either 8-bit or 9-bit data. The state of
the M bit in SCI control register 1 (SCC1) determines character length.
When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3) is
the ninth bit (bit 8).
12.5.2.2 Character Transmission
During an SCI transmission, the transmit shift register shifts a character
out to the PTE5/TxD pin. The SCI data register (SCDR) is the write-only
buffer between the internal data bus and the transmit shift register. To
initiate an SCI transmission:
1. Enable the SCI by writing a logic one to the enable SCI bit (ENSCI)
in SCI control register 1 (SCC1).
2. Enable the transmitter by writing a logic one to the transmitter
enable bit (TE) in SCI control register 2 (SCC2).
3. Clear the SCI transmitter empty bit by first reading SCI status
register 1 (SCS1) and then writing to the SCDR. In a DMA transfer,
the DMA automatically clears the SCTE bit by writing to the
SCDR.
4. Repeat step 3 for each subsequent transmission.
At the start of a transmission, transmitter control logic automatically
loads the transmit shift register with a preamble of logic ones. After the
preamble shifts out, control logic transfers the SCDR data into the
transmit shift register. A logic zero start bit automatically goes into the
least significant bit position of the transmit shift register. A logic one stop
bit goes into the most significant bit position.
The SCI transmitter empty bit, SCTE, in SCS1 becomes set when the
SCDR transfers a byte to the transmit shift register. The SCTE bit
indicates that the SCDR can accept new data from the internal data bus.
If the SCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the
SCTE bit generates a transmitter CPU interrupt request or a transmitter
DMA service request.
The SCTE bit generates a transmitter DMA service request if the DMA
transfer enable bit, DMATE, in SCI control register 3 (SCC3) is set.