
Keyboard Module (KB)
General Release Specification
MC68HC(7)08LN56 — Rev. 2.0
132
Keyboard Module (KB)
MOTOROLA
NONDISCLOSURE
AGREEMENT
REQUIRED
remains pending as long as any enabled keyboard interrupt pin is at
logic zero.
If the MODEK bit is clear, the keyboard interrupt pin is falling-edge-
sensitive only. With MODEK clear, a vector fetch or software clear
immediately clears the keyboard interrupt latch.
Reset clears the keyboard interrupt latch and the MODEK bit, clearing
the interrupt request even if a keyboard interrupt pin stays at logic zero.
The keyboard flag bit (KEYF) in the keyboard status and control register
can be used to see if a pending interrupt exists. The KEYF bit is not
affected by the keyboard interrupt mask bit (IMASKK) which makes it
useful in applications where polling is preferred.
To determine the logic level on a keyboard interrupt pin, use the data
direction register to configure the pin as an input and read the data
register.
NOTE:
Setting a keyboard interrupt enable bit (KBxIE) forces the corresponding
keyboard interrupt pin to be an input, overriding the data direction
register. However, the data direction register bit must be a logic zero for
software to read the pin.
9.5 Keyboard Initialization
When a keyboard interrupt pin is enabled, it takes time for the internal
pull-up to reach a logic one, so it is possible that an interrupt could occur
when the pin is initially enabled.
To prevent this, it is recommended that the keyboard interrupt be
masked with the IMASKK bit in the KBSCR register before enabling the
pin and that the ACKK bit be used to acknowledge the potential false
interrupt before setting IMASKK back to zero. An edge-only type of
interrupt can be acknowledged immediately after enabling the pin. An
edge- and level-triggered interrupt must be acknowledged after a delay
which is dependant on the external load.
Another way to avoid a false interrupt is to set the appropriate bit of port
A to an output driving a logic one, before enabling the keyboard input.