參數(shù)資料
型號: MC68HC05C9ECP
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40
封裝: PLASTIC, DIP-40
文件頁數(shù): 92/144頁
文件大小: 1628K
代理商: MC68HC05C9ECP
Resets
Computer Operating Properly (COP) Reset
MC68HC05C9E
Advance Information
MOTOROLA
Resets
51
N
O
N-D
I
SC
L
O
SU
R
E
AG
R
EEMENT
R
E
Q
U
IR
ED
COPE — COP Enable Bit
This bit is readable any time. COPE, CM1, and CM0 together may be
written with a single write, only once, after reset. This bit is cleared by
reset.
1 = COP enabled
0 = COP disabled
CM1 — COP Mode Bit 1
Used in conjunction with CM0 to establish the COP timeout period,
this bit is readable any time. COPE, CM1, and CM0 together may be
written with a single write, only once, after reset. This bit is cleared by
reset. See Table 5-1 for timeout period options.
CM0 — COP Mode Bit 0
Used in conjunction with CM1 to establish the COP timeout period,
this bit is readable any time. COPE, CM1, and CM0 together may be
written with a single write, only once, after reset. This bit is cleared by
reset. See Table 5-1 for timeout period options.
Bits 7–5 — Not Used
These bits always read as 0.
Table 5-1. COP Timeout Period
CM1
CM0
fOP/2
15 Divide By
Timeout Period
(fOSC = 2.0 MHz)
Timeout Period
(fOSC = 4.0 MHz)
0
1
32.77 ms
16.38 ms
0
1
4
131.07 ms
65.54 ms
1
0
16
524.29 ms
262.14 ms
1
64
2.097 s
1.048 s
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