參數(shù)資料
型號(hào)： MC68HC05C9AP
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁數(shù)： 143/160頁
文件大?。?/td> 4128K
代理商： MC68HC05C9AP
Serial Communications Interface (SCI)
SCI I/O Registers
MC68HC05C9A — Rev. 4.0
General Release Specification
Serial Communications Interface (SCI)
NON-DISCLOSURE
AGREEMENT
REQUIRED
ILIE — Idle Line Interrupt Enable
This read/write bit enables SCI interrupt requests when the IDLE bit
becomes set. Resets clear the ILIE bit.
1 = IDLE interrupt requests enabled
0 = IDLE interrupt requests disabled
TE — Transmitter Enable
Setting this read/write bit begins the transmission by sending a
preamble of 10 or 11 logic ones from the transmit shift register to the
PD1/TDO pin. Resets clear the TE bit.
1 = Transmission enabled
0 = Transmission disabled
RE — Receiver Enable
Setting this read/write bit enables the receiver. Clearing the RE bit
disables the receiver and receiver interrupts but does not affect the
receiver interrupt flags. Resets clear the RE bit.
1 = Receiver enabled
0 = Receiver disabled
RWU — Receiver Wakeup Enable
This read/write bit puts the receiver in a standby state. Typically, data
transmitted to the receiver clears the RWU bit and returns the receiver
to normal operation. The WAKE bit in SCCR1 determines whether an
idle input or an address mark brings the receiver out of standby state.
Reset clears the RWU bit.
1 = Standby state
0 = Normal operation
SBK — Send Break
Setting this read/write bit continuously transmits break codes in the
form of 10-bit or 11-bit groups of logic zeros. Clearing the SBK bit
stops the break codes and transmits a logic one as a start bit. Reset
clears the SBK bit.
1 = Break codes being transmitted
0 = No break codes being transmitted
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For More Information On This Product,
Go to: www.freescale.com
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