參數(shù)資料
型號: MC68HC05C9ACFN
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 4.2 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 101/160頁
文件大?。?/td> 783K
代理商: MC68HC05C9ACFN
Resets
RESET Pin
MC68HC05C9A Rev. 4.0
General Release Specification
MOTOROLA
Resets
45
NON-DISCLOSURE
AGREEMENT
REQUIRED
5.4 RESET Pin
The MCU is reset when a logic zero is applied to the RESET input for a
period of one and one-half machine cycles (tRL). However, in order to
differentiate between an external reset and an internal reset (generated
from the COP or clock monitor), any externally driven reset must be
active (logic zero) for at least eight tCYC.
Figure 5-2. Power-On Reset and RESET
RESET
OSC1
2
INTERNAL
CLOCK
1
INTERNAL
ADDRESS
BUS
1
V
DD
INTERNAL
DATA
BUS
1
t
RL
NEW
PCH
NEW
PCL
OP
CODe
OP
CODE
PCH
PCL
3
t
CYC
4064t
CYC
t
VDDR
DUMMY
3FFF
NEW
PC
NEW
PC
3FFE
NEW
PC
NEW
PC
3FFE
3FFF
3FFE
DUMMY
NOTES:
1. Internal timing signal and bus information are not available externally.
2. OSC1 line is not meant to represent frequency. It is only meant to represent time.
3. The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence.
4
4. RESET outputs VOL during 4064 power-on reset cycles.
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