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MOTOROLA
M68040 USER鈥橲 MANUAL
B-11
MC68EC040 REV2.3 (01/31/2000)
The PTEST and PFLUSH instructions should not be executed. Execution of the PTEST
instruction causes random bus cycles to occur. Execution of the PFLUSH instruction
produces indeterminate results. Neither instruction causes the MC68EC040 to generate an
exception.
The CPUSH and CINV instructions require special consideration. A page is dened as a
4-Kbyte block of external memory. The CPUSH and CINV page instruction opcodes can be
used to push or invalidate 4-Kbyte blocks of memory. The MC68EC040 does not support
8-Kbyte pages.
The MOVEC to URP and SRP instructions are not valid and will produce indeterminate
results. Each ACU has a status register and translation control register that replace the MMU
status register and translation control register of the MC68040. The MMU status register
opcode of the MOVEC instruction can modify the ACU status register. The MC68EC040
ACU status register does not provide additional functionality to the ACU and is only provided
for compatibility with the ACU MC68EC030 status register. The ACU status register may not
be implemented in future M68EC0X0 products.
B.7 MC68EC040 ELECTRICAL CHARACTERISTICS
The following paragraphs provide information on the maximum rating and thermal charac-
teristics for the MC68EC040 only. Refer to Appendix C MC68040V and MC68EC040V for
more information on electrical characteristics for the MC68EC040V. This section is subject
to change. For the most recent specications, contact a Motorola sales ofce or complete
the registration card at the end of this manual.
B.7.1 Maximum Ratings
B.7.2 Thermal Characteristics
Table 12-2.
Characteristic
Symbol
Value
Unit
This device contains protective
circuitry against damage due to
high static voltages or electrical
fields; however, it is advised that
normal precautions be taken to
avoid application of any voltages
higher
than
maximum-rated
voltages to this high-impedance
circuit. Reliablity of operation is
enhanced if unused inputs are
tied
to
an
appropriate
logic
voltage level (e.g., either GND or
VCC).
Supply Voltage
VCC
鈥�0.3 to +7.0
V
Input Voltage
Vin
鈥�0.5 to +7.0
V
Maximum Operating Junction Temperature
TJ
110
掳C
Minimum Operating Ambient Temperature
TA
0
掳C
Storage Temperature Range
Tstg
鈥�55 to 150
掳C
Characteristic
Symbol
Value
Rating
Thermal Resistance, Junction to Case鈥�
PGA Package
JC
3
掳C/W
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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MC68EC040FE25 鍒堕€犲晢:Motorola Inc 鍔熻兘鎻忚堪:
MC68EC040FE25A 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU 32B W/ CACHE RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁告摎绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:32 KB 鏁告摎 RAM 澶у皬:128 KB 鎺ュ彛椤炲瀷:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-324
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