- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨�(m菐i)璩�(m脿i)IC缍�(w菐ng) > PDF鐩寗4048 > MC68EC040FE20A (Freescale Semiconductor)IC MPU 32BIT 20MHZ 184-CQFP PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | MC68EC040FE20A |
| 寤犲晢锛� | Freescale Semiconductor |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 316/442闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MPU 32BIT 20MHZ 184-CQFP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 24 |
| 绯诲垪锛� | M680x0 |
| 铏曠悊鍣ㄩ(l猫i)鍨嬶細 | M680x0 32-浣� |
| 閫熷害锛� | 20MHz |
| 闆诲锛� | 5V |
| 瀹夎椤�(l猫i)鍨嬶細 | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 184-BCQFP |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 184-CQFP锛�31.3x31.3锛� |
| 鍖呰锛� | 鎵樼洡(p谩n) |
绗�1闋�(y猫)绗�2闋�(y猫)绗�3闋�(y猫)绗�4闋�(y猫)绗�5闋�(y猫)绗�6闋�(y猫)绗�7闋�(y猫)绗�8闋�(y猫)绗�9闋�(y猫)绗�10闋�(y猫)绗�11闋�(y猫)绗�12闋�(y猫)绗�13闋�(y猫)绗�14闋�(y猫)绗�15闋�(y猫)绗�16闋�(y猫)绗�17闋�(y猫)绗�18闋�(y猫)绗�19闋�(y猫)绗�20闋�(y猫)绗�21闋�(y猫)绗�22闋�(y猫)绗�23闋�(y猫)绗�24闋�(y猫)绗�25闋�(y猫)绗�26闋�(y猫)绗�27闋�(y猫)绗�28闋�(y猫)绗�29闋�(y猫)绗�30闋�(y猫)绗�31闋�(y猫)绗�32闋�(y猫)绗�33闋�(y猫)绗�34闋�(y猫)绗�35闋�(y猫)绗�36闋�(y猫)绗�37闋�(y猫)绗�38闋�(y猫)绗�39闋�(y猫)绗�40闋�(y猫)绗�41闋�(y猫)绗�42闋�(y猫)绗�43闋�(y猫)绗�44闋�(y猫)绗�45闋�(y猫)绗�46闋�(y猫)绗�47闋�(y猫)绗�48闋�(y猫)绗�49闋�(y猫)绗�50闋�(y猫)绗�51闋�(y猫)绗�52闋�(y猫)绗�53闋�(y猫)绗�54闋�(y猫)绗�55闋�(y猫)绗�56闋�(y猫)绗�57闋�(y猫)绗�58闋�(y猫)绗�59闋�(y猫)绗�60闋�(y猫)绗�61闋�(y猫)绗�62闋�(y猫)绗�63闋�(y猫)绗�64闋�(y猫)绗�65闋�(y猫)绗�66闋�(y猫)绗�67闋�(y猫)绗�68闋�(y猫)绗�69闋�(y猫)绗�70闋�(y猫)绗�71闋�(y猫)绗�72闋�(y猫)绗�73闋�(y猫)绗�74闋�(y猫)绗�75闋�(y猫)绗�76闋�(y猫)绗�77闋�(y猫)绗�78闋�(y猫)绗�79闋�(y猫)绗�80闋�(y猫)绗�81闋�(y猫)绗�82闋�(y猫)绗�83闋�(y猫)绗�84闋�(y猫)绗�85闋�(y猫)绗�86闋�(y猫)绗�87闋�(y猫)绗�88闋�(y猫)绗�89闋�(y猫)绗�90闋�(y猫)绗�91闋�(y猫)绗�92闋�(y猫)绗�93闋�(y猫)绗�94闋�(y猫)绗�95闋�(y猫)绗�96闋�(y猫)绗�97闋�(y猫)绗�98闋�(y猫)绗�99闋�(y猫)绗�100闋�(y猫)绗�101闋�(y猫)绗�102闋�(y猫)绗�103闋�(y猫)绗�104闋�(y猫)绗�105闋�(y猫)绗�106闋�(y猫)绗�107闋�(y猫)绗�108闋�(y猫)绗�109闋�(y猫)绗�110闋�(y猫)绗�111闋�(y猫)绗�112闋�(y猫)绗�113闋�(y猫)绗�114闋�(y猫)绗�115闋�(y猫)绗�116闋�(y猫)绗�117闋�(y猫)绗�118闋�(y猫)绗�119闋�(y猫)绗�120闋�(y猫)绗�121闋�(y猫)绗�122闋�(y猫)绗�123闋�(y猫)绗�124闋�(y猫)绗�125闋�(y猫)绗�126闋�(y猫)绗�127闋�(y猫)绗�128闋�(y猫)绗�129闋�(y猫)绗�130闋�(y猫)绗�131闋�(y猫)绗�132闋�(y猫)绗�133闋�(y猫)绗�134闋�(y猫)绗�135闋�(y猫)绗�136闋�(y猫)绗�137闋�(y猫)绗�138闋�(y猫)绗�139闋�(y猫)绗�140闋�(y猫)绗�141闋�(y猫)绗�142闋�(y猫)绗�143闋�(y猫)绗�144闋�(y猫)绗�145闋�(y猫)绗�146闋�(y猫)绗�147闋�(y猫)绗�148闋�(y猫)绗�149闋�(y猫)绗�150闋�(y猫)绗�151闋�(y猫)绗�152闋�(y猫)绗�153闋�(y猫)绗�154闋�(y猫)绗�155闋�(y猫)绗�156闋�(y猫)绗�157闋�(y猫)绗�158闋�(y猫)绗�159闋�(y猫)绗�160闋�(y猫)绗�161闋�(y猫)绗�162闋�(y猫)绗�163闋�(y猫)绗�164闋�(y猫)绗�165闋�(y猫)绗�166闋�(y猫)绗�167闋�(y猫)绗�168闋�(y猫)绗�169闋�(y猫)绗�170闋�(y猫)绗�171闋�(y猫)绗�172闋�(y猫)绗�173闋�(y猫)绗�174闋�(y猫)绗�175闋�(y猫)绗�176闋�(y猫)绗�177闋�(y猫)绗�178闋�(y猫)绗�179闋�(y猫)绗�180闋�(y猫)绗�181闋�(y猫)绗�182闋�(y猫)绗�183闋�(y猫)绗�184闋�(y猫)绗�185闋�(y猫)绗�186闋�(y猫)绗�187闋�(y猫)绗�188闋�(y猫)绗�189闋�(y猫)绗�190闋�(y猫)绗�191闋�(y猫)绗�192闋�(y猫)绗�193闋�(y猫)绗�194闋�(y猫)绗�195闋�(y猫)绗�196闋�(y猫)绗�197闋�(y猫)绗�198闋�(y猫)绗�199闋�(y猫)绗�200闋�(y猫)绗�201闋�(y猫)绗�202闋�(y猫)绗�203闋�(y猫)绗�204闋�(y猫)绗�205闋�(y猫)绗�206闋�(y猫)绗�207闋�(y猫)绗�208闋�(y猫)绗�209闋�(y猫)绗�210闋�(y猫)绗�211闋�(y猫)绗�212闋�(y猫)绗�213闋�(y猫)绗�214闋�(y猫)绗�215闋�(y猫)绗�216闋�(y猫)绗�217闋�(y猫)绗�218闋�(y猫)绗�219闋�(y猫)绗�220闋�(y猫)绗�221闋�(y猫)绗�222闋�(y猫)绗�223闋�(y猫)绗�224闋�(y猫)绗�225闋�(y猫)绗�226闋�(y猫)绗�227闋�(y猫)绗�228闋�(y猫)绗�229闋�(y猫)绗�230闋�(y猫)绗�231闋�(y猫)绗�232闋�(y猫)绗�233闋�(y猫)绗�234闋�(y猫)绗�235闋�(y猫)绗�236闋�(y猫)绗�237闋�(y猫)绗�238闋�(y猫)绗�239闋�(y猫)绗�240闋�(y猫)绗�241闋�(y猫)绗�242闋�(y猫)绗�243闋�(y猫)绗�244闋�(y猫)绗�245闋�(y猫)绗�246闋�(y猫)绗�247闋�(y猫)绗�248闋�(y猫)绗�249闋�(y猫)绗�250闋�(y猫)绗�251闋�(y猫)绗�252闋�(y猫)绗�253闋�(y猫)绗�254闋�(y猫)绗�255闋�(y猫)绗�256闋�(y猫)绗�257闋�(y猫)绗�258闋�(y猫)绗�259闋�(y猫)绗�260闋�(y猫)绗�261闋�(y猫)绗�262闋�(y猫)绗�263闋�(y猫)绗�264闋�(y猫)绗�265闋�(y猫)绗�266闋�(y猫)绗�267闋�(y猫)绗�268闋�(y猫)绗�269闋�(y猫)绗�270闋�(y猫)绗�271闋�(y猫)绗�272闋�(y猫)绗�273闋�(y猫)绗�274闋�(y猫)绗�275闋�(y猫)绗�276闋�(y猫)绗�277闋�(y猫)绗�278闋�(y猫)绗�279闋�(y猫)绗�280闋�(y猫)绗�281闋�(y猫)绗�282闋�(y猫)绗�283闋�(y猫)绗�284闋�(y猫)绗�285闋�(y猫)绗�286闋�(y猫)绗�287闋�(y猫)绗�288闋�(y猫)绗�289闋�(y猫)绗�290闋�(y猫)绗�291闋�(y猫)绗�292闋�(y猫)绗�293闋�(y猫)绗�294闋�(y猫)绗�295闋�(y猫)绗�296闋�(y猫)绗�297闋�(y猫)绗�298闋�(y猫)绗�299闋�(y猫)绗�300闋�(y猫)绗�301闋�(y猫)绗�302闋�(y猫)绗�303闋�(y猫)绗�304闋�(y猫)绗�305闋�(y猫)绗�306闋�(y猫)绗�307闋�(y猫)绗�308闋�(y猫)绗�309闋�(y猫)绗�310闋�(y猫)绗�311闋�(y猫)绗�312闋�(y猫)绗�313闋�(y猫)绗�314闋�(y猫)绗�315闋�(y猫)鐣�(d膩ng)鍓嶇316闋�(y猫)绗�317闋�(y猫)绗�318闋�(y猫)绗�319闋�(y猫)绗�320闋�(y猫)绗�321闋�(y猫)绗�322闋�(y猫)绗�323闋�(y猫)绗�324闋�(y猫)绗�325闋�(y猫)绗�326闋�(y猫)绗�327闋�(y猫)绗�328闋�(y猫)绗�329闋�(y猫)绗�330闋�(y猫)绗�331闋�(y猫)绗�332闋�(y猫)绗�333闋�(y猫)绗�334闋�(y猫)绗�335闋�(y猫)绗�336闋�(y猫)绗�337闋�(y猫)绗�338闋�(y猫)绗�339闋�(y猫)绗�340闋�(y猫)绗�341闋�(y猫)绗�342闋�(y猫)绗�343闋�(y猫)绗�344闋�(y猫)绗�345闋�(y猫)绗�346闋�(y猫)绗�347闋�(y猫)绗�348闋�(y猫)绗�349闋�(y猫)绗�350闋�(y猫)绗�351闋�(y猫)绗�352闋�(y猫)绗�353闋�(y猫)绗�354闋�(y猫)绗�355闋�(y猫)绗�356闋�(y猫)绗�357闋�(y猫)绗�358闋�(y猫)绗�359闋�(y猫)绗�360闋�(y猫)绗�361闋�(y猫)绗�362闋�(y猫)绗�363闋�(y猫)绗�364闋�(y猫)绗�365闋�(y猫)绗�366闋�(y猫)绗�367闋�(y猫)绗�368闋�(y猫)绗�369闋�(y猫)绗�370闋�(y猫)绗�371闋�(y猫)绗�372闋�(y猫)绗�373闋�(y猫)绗�374闋�(y猫)绗�375闋�(y猫)绗�376闋�(y猫)绗�377闋�(y猫)绗�378闋�(y猫)绗�379闋�(y猫)绗�380闋�(y猫)绗�381闋�(y猫)绗�382闋�(y猫)绗�383闋�(y猫)绗�384闋�(y猫)绗�385闋�(y猫)绗�386闋�(y猫)绗�387闋�(y猫)绗�388闋�(y猫)绗�389闋�(y猫)绗�390闋�(y猫)绗�391闋�(y猫)绗�392闋�(y猫)绗�393闋�(y猫)绗�394闋�(y猫)绗�395闋�(y猫)绗�396闋�(y猫)绗�397闋�(y猫)绗�398闋�(y猫)绗�399闋�(y猫)绗�400闋�(y猫)绗�401闋�(y猫)绗�402闋�(y猫)绗�403闋�(y猫)绗�404闋�(y猫)绗�405闋�(y猫)绗�406闋�(y猫)绗�407闋�(y猫)绗�408闋�(y猫)绗�409闋�(y猫)绗�410闋�(y猫)绗�411闋�(y猫)绗�412闋�(y猫)绗�413闋�(y猫)绗�414闋�(y猫)绗�415闋�(y猫)绗�416闋�(y猫)绗�417闋�(y猫)绗�418闋�(y猫)绗�419闋�(y猫)绗�420闋�(y猫)绗�421闋�(y猫)绗�422闋�(y猫)绗�423闋�(y猫)绗�424闋�(y猫)绗�425闋�(y猫)绗�426闋�(y猫)绗�427闋�(y猫)绗�428闋�(y猫)绗�429闋�(y猫)绗�430闋�(y猫)绗�431闋�(y猫)绗�432闋�(y猫)绗�433闋�(y猫)绗�434闋�(y猫)绗�435闋�(y猫)绗�436闋�(y猫)绗�437闋�(y猫)绗�438闋�(y猫)绗�439闋�(y猫)绗�440闋�(y猫)绗�441闋�(y猫)绗�442闋�(y猫)
MOTOROLA
M68040 USER鈥橲 MANUAL
B-7
MC68EC040 REV2.3 (01/31/2000)
ADDRESS MASK eld equals $0F, the W-bit is set to one, and the S-eld = $1. The inclusion
of independent ACRs in both the instruction ACU (IACU) and data ACU (DACU provides an
exception to the merged instruction and data address space, allowing different access con-
trol for instruction and operand accesses. Also, since the instruction memory unit is only
used for instruction prefetches, different instruction and data ACRs can cause PC relative
operand fetches to be translated differently from instruction prefetches.
Matching either of the ACRs in a corresponding ACU during an access to a memory unit
completes the access with the ACU. If both registers match, the access uses the xACR0 sta-
tus bits. Addresses are passed through without translation if there is no match in the ACRs
and no table search occurs. The MC68EC040 does not perform table searches.
B.3.3 Effect of RSTI on the ACU
When the assertion of the reset input (RSTI) signal resets the MC68EC040, the E-bits of the
ACRs are cleared, disabling address access control.
B.4 SPECIAL MODES OF OPERATION
This part of the M68040 User's Manual does not apply to the MC68EC040. The
MC68EC040 does not sample the IPL2鈥揑PL0, CDIS, JS0 (DLE on the MC68040), or JS1
(MDIS on the MC68040) pins on the rising edge of RSTI.
An external device asserts RSTI to reset the processor. When power is applied to the sys-
tem, external circuitry should assert RSTI for a minimum of 10 BCLK cycles after VCC is
within tolerance. Figure B-5 is a functional timing diagram of the power-on reset operation,
illustrating the relationships between VCC, RSTI, and bus signals. The BCLK and PCLK
clock signals are required to be stable by the time VCC reaches the minimum operating spec-
ication. RSTI is internally synchronized for two BCLKS before being used, and must meet
the specied setup and hold times to BCLK (specications #51 and #52 in MC68EC040
Electrical Characteristics) only if recognition by a specic BCLK rising edge is required.
Once RSTI is negated, the processor is internally held in reset for another 128 clock cycles.
During the reset period, all three-statable signals are three-stated, and the rest are driven to
their inactive state. Once the internal reset signal negates, all bus signals remain in a
high-impedance state until the processor is granted the bus. After this, the rst bus cycle for
reset exception processing begins. In Figure B-6, the processor assumes implicit ownership
of the bus before the rst bus cycle begins. The levels on the CDIS, JS1 (MDIS on the
MC68040), and IPL2鈥揑PL0 signals are not sampled when RSTI is negated.
For processor resets after the initial power-on reset, should be asserted for at least 10 clock
periods. Figure B-6 illustrates timing associated with a reset when the processor is executing
bus cycles. Note that BB and TIP (and TA driven during a snooped access) are asserted
before transitioning to a three-state level. Processor reset causes any bus cycle in progress
to terminate as if TA or TEA had been asserted. Also, the processor initializes registers
appropriately for a reset exception.
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| AMM43DRAH | CONN EDGECARD 86POS .156 R/A |
| XC4044XL-2HQ240I | IC FPGA I-TEMP 3.3V 2SPD 240HQFP |
| XC4044XL-2HQ240C | IC FPGA C-TEMP 3.3V 2SPD 240HQFP |
| MC7448VU1000LD | IC MPU RISC 32BIT 360-FCCBGA |
| MPC8535BVTANGA | MPU POWERQUICC III 783FCPBGA |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| MC68EC040FE20B | 鍒堕€犲晢:MOTOROLA 鍒堕€犲晢鍏ㄧū(ch膿ng):Motorola, Inc 鍔熻兘鎻忚堪:M68000-compatible, high-performance, 32-bit microprocessors |
| MC68EC040FE25 | 鍒堕€犲晢:Motorola Inc 鍔熻兘鎻忚堪: |
| MC68EC040FE25A | 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU 32B W/ CACHE RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤�(l猫i)鍨�:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-324 |
| MC68EC040FE25B | 鍒堕€犲晢:MOTOROLA 鍒堕€犲晢鍏ㄧū(ch膿ng):Motorola, Inc 鍔熻兘鎻忚堪:M68000-compatible, high-performance, 32-bit microprocessors |
| MC68EC040FE33A | 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU 32B W/ CACHE RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤�(l猫i)鍨�:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-324 |
鐧�(f膩)甯冪穵鎬ラ噰璩�(g貌u)锛�3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京(f霉)銆�
