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鍨嬭櫉锛� MC68EC040FE20A
寤犲晢锛� Freescale Semiconductor
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鎻忚堪锛� IC MPU 32BIT 20MHZ 184-CQFP
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绯诲垪锛� M680x0
铏曠悊鍣ㄩ鍨嬶細 M680x0 32-浣�
閫熷害锛� 20MHz
闆诲锛� 5V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 184-BCQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 184-CQFP锛�31.3x31.3锛�
鍖呰锛� 鎵樼洡
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11-16
M68040 USER鈥橲 MANUAL
MOTOROLA
Maximum power dissipation in the large buffer mode occurs for output:
Low:
Pllb = I2R = (49.6 mA)2 x 6 = 14.8 mW
High:
Phlb = I2R = (50.8 mA)2 x 12 = 30.1 mW
Similar calculations for unterminated small buffers yield:
I = 5 mA (by spec)
and
P = I2R = (5 mA)2 x 25
so
Phsb = 0.625 mW
Plsb = 0.625 mW
Assuming that the duty cycle of output j is driving a valid logic value instead of being
three-stated as given by DCj, then the following equation approximates total average
power dissipation in the output buffers:
Number of
Outputs Used
ITotal =
鈭�
j = 1
(Ij 脳 DCj)2 脳 Reffj
I j and Zoj are calculated for every pin as illustrated above. In practice the above
summation is carried out by groups of pins instead of individual pins.
Motorola has calculated the values for DCj for typical situations. On an average clock
there will be 37.8 pins high, 41.5 pins low, and 11.7 pins three-stated. The following
examples demonstrate how to calculate the power dissipation that is added to small buffer
power dissipation numbers, assuming a termination as illustrated in Figure 11-18.
a. For the numbers listed in this section in a large buffer design with no caching.
P = (Number of Pins High)
脳 (Phlb) + (Number of Pins Low) 脳 (Pllb)
= 37.8 Pins
脳 30.1 mW per Pin + 41.5 Pins 脳 14.8 mW per Pin
= 1.75 W
b. For a single bus master system in a large buffer design with no caching or snooping
and only standard features (i.e., TLN, UPA, BR, BB, LOCK, LOCKE, CIOUT, TIP, MI,
TDO, IPEND, PST not used):
P = (Number of Pins High)
脳 (Phlb) + (Number of Pins Low) 脳 (Pllb)
= 29.8 Pins
脳 30.1 mW per Pin + 34.5 Pins 脳 14.8 mW per Pin
= 1.41 W
c. For the example b system with copyback caching, assuming 85% cache hit rate:
P = (29.8 Pins
脳 30.1 mW per Pin + 34.5 Pins 脳 14.8 mW per Pin) 脳 (1 鈥� 0.85)
= 0.21 W
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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MC68EC040FE20B 鍒堕€犲晢:MOTOROLA 鍒堕€犲晢鍏ㄧū:Motorola, Inc 鍔熻兘鎻忚堪:M68000-compatible, high-performance, 32-bit microprocessors
MC68EC040FE25 鍒堕€犲晢:Motorola Inc 鍔熻兘鎻忚堪:
MC68EC040FE25A 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU 32B W/ CACHE RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤炲瀷:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-324
MC68EC040FE25B 鍒堕€犲晢:MOTOROLA 鍒堕€犲晢鍏ㄧū:Motorola, Inc 鍔熻兘鎻忚堪:M68000-compatible, high-performance, 32-bit microprocessors
MC68EC040FE33A 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU 32B W/ CACHE RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤炲瀷:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-324