參數(shù)資料
型號(hào): MC56F8245MLD
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 57/88頁(yè)
文件大?。?/td> 0K
描述: DSC 48K FLASH 60MHZ 44-LQFP
標(biāo)準(zhǔn)包裝: 160
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 60MHz
連通性: CAN,I²C,LIN,SCI,SPI
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 35
程序存儲(chǔ)器容量: 48KB(24K x 16)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 3K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b,D/A 1x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 44-LQFP
包裝: 管件
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Specifications
Freescale Semiconductor
60
7.17
Reset, Stop, Wait, Mode Select, and Interrupt Timing
NOTE
All address and data buses described here are internal.
Figure 19. GPIO Interrupt Timing (Negative Edge-Sensitive)
7.18
Queued Serial Peripheral Interface (SPI) Timing
Table 33. Reset, Stop, Wait, Mode Select, and Interrupt Timing1,2
1 In the formulas, T = system clock cycle and T
osc = oscillator clock cycle. For an operating frequency of 32 MHz, T = 31.25 ns.
At 4 MHz (used coming out of reset and stop modes), T = 250 ns.
2 Parameters listed are guaranteed by design.
Characteristic
Symbol
Typical Min
Typical Max
Unit
See Figure
Minimum RESET Assertion Duration 3
3 This minimum number guarantees that a reliable reset occurs.
tRA
4T
ns
Minimum GPIO pin Assertion for Interrupt
tIW
2T
ns
RESET deassertion to First Address Fetch
tRDA
96TOSC + 64T
97TOSC + 65T
ns
Delay from Interrupt Assertion to Fetch of first
instruction (exiting Stop)
tIF
—6T
ns
Table 34. SPI Timing1
Characteristic
Symbol
Min
Max
Unit
Refer to
Cycle time
Master
Slave
tC
125
62.5
ns
Enable lead time
Master
Slave
tELD
31
ns
Enable lag time
Master
Slave
tELG
125
ns
Clock (SCK) high time
Master
Slave
tCH
50
31
ns
Clock (SCK) low time
Master
Slave
tCL
50
31
ns
GPIO pin
(Input)
tIW
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