參數(shù)資料
型號(hào): MC56F8245MLD
廠商: Freescale Semiconductor
文件頁數(shù): 27/88頁
文件大?。?/td> 0K
描述: DSC 48K FLASH 60MHZ 44-LQFP
標(biāo)準(zhǔn)包裝: 160
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 60MHz
連通性: CAN,I²C,LIN,SCI,SPI
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 35
程序存儲(chǔ)器容量: 48KB(24K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 3K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b,D/A 1x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 44-LQFP
包裝: 管件
Memory Maps
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Freescale Semiconductor
33
Figure 8. 56F8245/46 Dual Port RAM Map
4.4
Interrupt Vector Table and Reset Vector
The location of the vector table is determined by the vector base address register (VBA). The value in this register is used as
the upper 14 bits of the interrupt vector VAB[20:0]. The lower seven bits are determined based on the highest priority interrupt
and are then appended to VBA before presenting the full VAB to the core. Refer to the device’s reference manual for details.
The reset startup addresses of 56F824x and 56F825x are different.
The 56F825x’s startup address is located at 0x00 0000. The reset value of VBA is reset to a value of 0x0000 that
corresponds to the address 0x00 0000.
Table 11. 56F8245/56 Data Memory Map1
1 All addresses are 16-bit word addresses.
Begin/End Address
Memory Allocation
X:0xFF FFFF
X:0xFF FF00
EOnCE
256 locations allocated
X:0xFF FEFF
X:0x01 0000
RESERVED
X:0x00 FFFF
X:0x00 F000
On-Chip Peripherals
4096 locations allocated
X:0x00 EFFF
X:0x00 8C00
RESERVED
X:0x00 8BFF
X:0x00 8000
On-Chip Data RAM Alias
X:0x00 7FFF
X:0x00 0C00
RESERVED
X:0x00 0BFF
X:0x00 0000
On-Chip Data RAM
6KB2
2 This RAM is shared with program space starting at P: 0x00 8000. See Figure 8.
Reserved
RAM
Reserved
EOnCE
Peripherals
Reserved
RAM
Dual Port RAM
Program
Data
Flash
0x00 0000
0x00 0C00
0x00 F000
0x01 0000
0xFF FF00
0x00 0000
0x00 8000
0x00 8C00
RAM Alias
0x00 8000
Reserved
0x00 2000
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