參數(shù)資料
型號: MC56F8245MLD
廠商: Freescale Semiconductor
文件頁數(shù): 22/88頁
文件大?。?/td> 0K
描述: DSC 48K FLASH 60MHZ 44-LQFP
標(biāo)準(zhǔn)包裝: 160
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 60MHz
連通性: CAN,I²C,LIN,SCI,SPI
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 35
程序存儲器容量: 48KB(24K x 16)
程序存儲器類型: 閃存
RAM 容量: 3K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b,D/A 1x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 44-LQFP
包裝: 管件
Memory Maps
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Freescale Semiconductor
29
4
Memory Maps
4.1
Introduction
The MC56F825x/MC56F824x device is based on the 56800E core. It uses a dual Harvard-style architecture with two
independent memory spaces for data and program. On-chip RAM is shared by both data and program spaces; flash memory is
used only in program space.
This section provides memory maps for:
Program address space, including the interrupt vector table
Data address space, including the EOnCE memory and peripheral memory maps
On-chip memory sizes for the device are summarized in Table 6. Flash memories’ restrictions are identified in the “Use
Restrictions” column of Table 6.
GPIOF6
(TB2)
(PWM3X)
58
Input/
Output
Input/
Output
Input/
Output
Input,
internal
pullup
enabled
Port F GPIO — This GPIO pin can be individually programmed as
an input or output pin.
TB2 — Quad timer module B channel 2 input/output.
PWM3X — Enhanced PWM submodule 3 output X or input capture
X
After reset, the default state is GPIOF6.
GPIOF7
(TB3)
59
Input/
Output
Input/
Output
Input,
internal
pullup
enabled
Port F GPIO — This GPIO pin can be individually programmed as
an input or output pin.
TB3 — Quad timer module B channel 3 input/output.
After reset, the default state is GPIOF7.
GPIOF8
(RXD0)
(TB1)
6
Input/
Output
Input
Input/
Output
Input,
internal
pullup
enabled
Port F GPIO — This GPIO pin can be individually programmed as
an input or output pin.
RXD0 — The SCI0 receive data input.
TB1 — Quad timer module B channel 1 input/output.
After reset, the default state is GPIOF8.
1
If CLKIN is selected as the device’s external clock input, both the GPS_C0 bit in GPS1 and the EXT_SEL bit in the OCCS
oscillator control register (OSCTL) must be set. In this case, it is also recommended to power down the crystal oscillator.
Table 5. MC56F825x/MC56F824x Signal and Package Information (continued)
Signal
Name
44
LQFP
48
LQFP
64
LQFP
Type
State
During
Reset
Signal Description
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