參數(shù)資料
型號(hào): MC56F8122VFAE
廠商: Freescale Semiconductor
文件頁數(shù): 9/136頁
文件大?。?/td> 0K
描述: IC DSP 16BIT 40MHZ 48-LQFP
標(biāo)準(zhǔn)包裝: 250
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 40MHz
連通性: SCI,SPI
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 21
程序存儲(chǔ)器容量: 32KB(16K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 4K x 16
電壓 - 電源 (Vcc/Vdd): 2.25 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 6x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 48-LQFP
包裝: 托盤
產(chǎn)品目錄頁面: 734 (CN2011-ZH PDF)
56F8322 Techncial Data, Rev. 16
106
Freescale Semiconductor
Preliminary
Table 10-6 Power-On Reset Low Voltage Parameters
Characteristic
Symbol
Min
Typ
Max
Units
POR Trip Point Rising1
1. Both VEI2.5 and VEI3.3 thresholds must be met for POR to be released on power-up.
PORR
———
V
POR Trip Point Falling
PORF
1.75
1.8
1.9
V
LVI, 2.5V Supply, trip point2
2. When VDD_CORE drops below VEI2.5, an interrupt is generated.
VEI2.5
—2.14—
V
LVI, 3.3V supply, trip point3
3. When VDD_CORE drops below VEI3.3, an interrupt is generated.
VEI3.3
—2.7
V
Bias Current
I bias
—110
130
μA
Table 10-7 Current Consumption per Power Supply Pin (Typical)
On-Chip Regulator Enabled (OCR_DIS = Low)
Mode
IDD_IO
1
1. No Output Switching (Output switching current can be estimated from I = CVf for each output)
2. Includes Processor Core current supplied by internal voltage regulator
IDD_ADC
IDD_OSC_PLL
Test Conditions
RUN1_MAC
115mA
25mA
2.5mA
60MHz Device Clock
All peripheral clocks are enabled
Continuous MAC instructions with fetches from
Data RAM
ADC powered on and clocked
Wait3
60mA
35
μA2.5mA
60MHz Device Clock
All peripheral clocks are enabled
ADC powered off
Stop1
5.7mA
0
μA360μA
4MHz Device Clock
All peripheral clocks are off
Relaxation oscillator is on
ADC powered off
PLL powered off
Stop2
5mA
0
μA145μA
Relaxation oscillator is off
All peripheral clocks are off
ADC powered off
PLL powered off
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