參數(shù)資料
型號： MC56F8122VFAE
廠商： Freescale Semiconductor
文件頁數(shù)： 131/136頁
文件大?。?/td> 0K
描述： IC DSP 16BIT 40MHZ 48-LQFP
標(biāo)準(zhǔn)包裝： 250
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 40MHz
連通性： SCI，SPI
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 21
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
RAM 容量： 4K x 16
電壓 - 電源 (Vcc/Vdd)： 2.25 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 6x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 48-LQFP
包裝： 托盤
產(chǎn)品目錄頁面： 734 (CN2011-ZH PDF)
56F8322 Techncial Data, Rev. 16
94
Freescale Semiconductor
Preliminary
6.8 Stop and Wait Mode Disable Function
Figure 6-16 Internal Stop Disable Circuit
The 56800E core contains both STOP and WAIT instructions. Both put the CPU to sleep. For lowest
power consumption in Stop mode, the PLL can be shut down. This must be done explicitly before entering
Stop mode, since there is no automatic mechanism for this. When the PLL is shut down, the 56800E
system clock must be set equal to the prescaler output.
Some applications require the 56800E STOP and WAIT instructions be disabled. To disable those
instructions, write to the SIM control register (SIM_CONTROL) described in Section 6.5.1 . This
procedure can be on either a permanent or temporary basis. Permanently assigned applications last only
until their next reset.
6.9 Resets
The SIM supports four sources of reset. The two asynchronous sources are the external RESET pin and
the Power-On Reset (POR). The two synchronous sources are the software reset, which is generated within
the SIM itself, by writing to the SIM_CONTROL register, and the COP reset.
Reset begins with the assertion of any of the reset sources. Release of reset to various blocks is sequenced
to permit proper operation of the device. A POR reset is declared when reset is removed and any of the
three voltage detectors (1.8V POR, 2.2V core voltage, or 2.7V I/O voltage) indicate a low supply voltage
condition. POR will continue to be asserted until all voltage detectors indicate a stable supply is available
(note that as power is removed POR is not declared until the 1.8V core voltage threshold is reached.) A
POR reset is then extended for 64 clock cycles to permit stabilization of the clock source, followed by a
32 clock window in which SIM clocking is initiated. It is then followed by a 32 clock window in which
peripherals are released to implement Flash security, and, finally, followed by a 32 clock window in which
the core is initialized. After completion of the described reset sequence, application code will begin
execution.
Resets may be asserted asynchronously, but are always released internally on a rising edge of the system
clock.
D-FLOP
DQ
C
D-FLOP
D
Q
C R
56800E
STOP_DIS
Permanent
Disable
Reprogrammable
Disable
Clock
Select
Reset
D
Note: Wait disable circuit is similar
相關(guān)PDF資料
PDF描述
VE-B5J-IX-B1 CONVERTER MOD DC/DC 36V 75W
MC908QC16VDRE IC MCU 8BIT 16K FLASH 28-TSSOP
TVP5150APBS IC NTSC/PAL/SECAM DECODER 32TQFP
MCF51JE256VMB IC MCU 256K COLDF 81-PBGA
VE-B5J-IW-B1 CONVERTER MOD DC/DC 36V 100W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC56F8123 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:16-bit Hybrid Controllers
MC56F8123VFB 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:16-bit Hybrid Controllers
MC56F8123VFBE 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16 BIT HYBRID CONTROLLER RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
MC56F8135 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controller
MC56F8135E 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controller
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*