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參數資料
| 型號： | MC34118DW |
| 廠商： | Freescale Semiconductor |
| 文件頁數： | 3/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VOICE SWITCH SPKPHONE 28-SOIC |
| 標準包裝： | 26 |
| 功能： | 語音切換式揚聲電話 |
| 電路數： | 1 |
| 電源電壓： | 3.5 V ~ 6.5 V |
| 電流 - 電源： | 5.5mA |
| 工作溫度： | -20°C ~ 60°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 28-SOIC W |
| 包裝： | 管件 |
| 包括： | 背景噪聲監(jiān)視器，芯片禁用，撥號音調檢測器，驅動器放大器，電平檢測器，麥克風放大器，靜音 |
MC34118
MOTOROLA
11
With an appropriate choice of an input coupling capacitor to
the low pass filter, a band pass filter is formed.
FI
R2
0.01
0
-- 3.0
-- 30
fN =
1
2π
1
C1C2R2
FOR R1 = R2
MC34118
Vin
R1
13 k
4.0 k
20 k
220 k
VB
Figure 9. Low Pass Filter
13 k
FO
0.001
C2
C1
fN
+1
POWER SUPPLY, VB, AND CHIP DISABLE
The power supply voltage at VCC (Pin 4) is to be between
3.5 and 6.5 volts for normal operation, with reduced opera-
tion possible down to 2.8 volts (see Figure 15 and the AGC
section). The power supply current is shown in Figure 18 for
both the power--up and power--down mode.
The output voltage at VB (Pin 15 is ≈(VCC -- 0.7)/2, and
provides the ac ground for the system. The output imped-
ance at VB is ≈400 (see Figure 19), and in conjunction
with the external capacitor at VB, forms a low pass filter for
power supply rejection. Figure 20 indicates the amount of re-
jection with different capacitors. The choice of capacitor is
application dependent based on whether the circuit is pow-
ered by the telephone line or a power supply.
Since VB biases the microphone and hybrid amplifiers, the
amount of supply rejection at their outputs is directly related
to the rejection at VB, as well as their respective gains. Fig-
ure 21 depicts this graphically.
The Chip Disable (Pin 3) permits powering down the IC to
conserve power and/or for muting purposes. With CD
≤ 0.8 volts, normal operation is in effect. With CD ≥ 2.0 volts
and ≤ VCC, the IC is powered down. In the powered down
mode, the microphone and the hybrid amplifiers are dis-
abled, and their outputs go to a high impedance state. Addi-
tionally, the bias is removed from the level detectors. The
bias is not removed from the filter (Pins 1, 2), the attenuators
(Pins 8, 9, 21, 22), or from Pins 13, 14, and 15 (the attenua-
tors are disabled, however, and will not pass a signal). The
input impedance at CD is typically 90 k, has a threshold of
≈1.5 volts, and the voltage at this pin must be kept within the
range of ground and VCC (see Figure 17). If CD is not used,
the pin should be grounded.
Figure 10. Attenuator Gain versus VCT (Pin 14)
Figure 11. Level Detector DC Transfer Characteristics
-- 240
+10
0
-- 10
-- 20
-- 30
-- 40
-- 160
-- 80
0
+ 80
+ 160
+ 240
-- 50
TRANSMIT
ATTENUATOR
0
140
120
100
80
60
40
-- 20
-- 40
-- 60
-- 80
-- 100
20
0
VCT -- VB (mV)
DC INPUT CURRENT (A)
RECEIVE
ATTENUATOR
VCC ≥ 3.5 V
VB
4.0
A
350
2.0 F
Vout
(RLO1, RLO2
TLO1, TLO2)
+
--
Iin
(RLI1, RLI2
TLI1, TLI2)
GAIN
(dB)
OUTPUT
CHANGE
(mV)
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