參數(shù)資料
型號(hào)： MC33984PNA
廠商： Motorola, Inc.
英文描述： Dual Intelligent High-Current Self-Protected Silicon High-Side Switch (4.0 mз)
中文描述： 雙智能大電流的自我保護(hù)硅高邊開關(guān)（4.0mз）
文件頁(yè)數(shù)： 8/28頁(yè)
文件大小： 492K
代理商： MC33984PNA
33984
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
16
Figure 7. Single 8-Bit Word SPI Communication
Figure 8. Multiple 8-Bit Word SPI Communication
Serial Input Communication
SPI communication is accomplished using 8-bit messages.
A message is transmitted by the MCU starting with the MSB,
D7, and ending with the LSB, D0 (Table 1). Each incoming
command message on the SI terminal can be interpreted using
the following bit assignments: the MSB (D7) is the watchdog bit
and in some cases a register address bit common to both
outputs or specific to an output; the next three bits, D6:D4, are
used to select the command register; and the remaining four
bits, D3:D0, are used to configure and control the outputs and
their protection features.
Multiple messages can be transmitted in succession to
accommodate those applications where daisy chaining is
desirable, or to confirm transmitted data, as long as the
messages are all multiples of eight bits. Any attempt made to
latch in a message that is not eight bits will be ignored.
The 33984 has defined registers, which are used to
configure the device and to control the state of the output.
Table 2 page 17, summarizes the SI registers. The registers
are addressed via D6:D4 of the incoming SPI word (Table 1).
CSB
SI
SCLK
D7
D1
D2
D3
D4
D5
D6
D0
OD7
OD6
OD1
OD2
OD3
OD4
OD5
NOTES:
OD0
SO
1.
RSTB is in a logic 1 state during the above operation.
2.
D0, D1, D2, ..., and D7 relate to the most recent ordered entry of data into the SPSS
3.
OD0, OD1, OD2, ..., and OD7 relate to the first 8 bits of ordered fault and status data out
of the device.
CS
SO
RST
1. RST is a logic [1] state during the above operation.
2. D7:D0 relate to the most recent ordered entry of data into the device.
3. OD7:OD0 relate to the first 8 bits of ordered fault and status data out of the device.
Notes
CS B
SI
SC L K
D7
D1 *
D2 *
D5 *
D6 *
D7 *
D0
D1
D6
D5
D2
D0 *
OD 5
OD 6
OD 7
D6
D7
OD 0
OD 1
OD 2
D1
D2
D5
F I G U R E 4 b .
M U L T IP L E 8 b i t W O R D S P I C O M M U N IC A T IO N
NO T E S :
D0
SO
1 .
R S T B i s i n a l ogi c 1 s t a t e dur i ng t h e abov e oper at i on.
2 .
D 0 , D 1 , D 2 , .. ., a n d D 7 r e l a te to th e m o s t r e c e n t o r d e r e d e n t r y o f d a ta i n to th e S P S S
3 .
O D 0, O D 1, O D 2, . . . , an d O D 7 r e l a t e t o t he f i r s t 8 b i t s o f or der ed f aul t and s t at u s dat a ou t of t he dev i c e.
4 .
O D 0, O D 1, O D 2, . . . , an d O D 7 r epr es ent t he f i r s t 8 bi t s o f o r d e r ed f aul t a n d s t at u s da t a out of t he S P S S
CS
SCLK
SI
SO
RST
1. RST is a logic [1] state during the above operation.
2. D7:D0 relate to the most recent ordered entry of data into the device.
4. OD7:OD0 relate to the first 8 bits of ordered fault and status data out of the device.
Notes
3. D7*:D0* relate to the previous 8 bits (last command word) of data that was previously shifted into the device.
Table 1. SI Message Bit Assignment
Bit Sig SI Msg Bit
Message Bit Description
MSB
D7
Register address bit for output selection. Also
used for Watchdog: toggled to satisfy
watchdog requirements.
D6:D4
Register address bits.
D3:D1
Used to configure the inputs, outputs, and the
device protection features and SO status
content.
LSB
D0
Used to configure the inputs, outputs, and the
device protection features and SO status
content.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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