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參數(shù)資料
| 型號： | MC33984PNA |
| 廠商： | Motorola, Inc. |
| 英文描述： | Dual Intelligent High-Current Self-Protected Silicon High-Side Switch (4.0 mз) |
| 中文描述： | 雙智能大電流的自我保護硅高邊開關(guān)（4.0mз） |
| 文件頁數(shù)： | 4/28頁 |
| 文件大?。?/td> | 492K |
| 代理商： | MC33984PNA |
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33984
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
12
DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V
≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SPI INTERFACE CHARACTERISTICS
Recommended Frequency of SPI Operation
fSPI
–
3.0
MHz
Required Low State Duration for RST (Note 24)
tWRST
–
50
350
ns
Rising Edge of CS to Falling Edge of CS (Required Setup Time) (Note 25)
tCS
–
300
ns
Rising Edge of RST to Falling Edge of CS (Required Setup Time) (Note 25)
tENBL
–
5.0
s
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (Note 25)
tLEAD
–
50
167
ns
Required High State Duration of SCLK (Required Setup Time) (Note 25)
tWSCLKh
–
167
ns
Required Low State Duration of SCLK (Required Setup Time) (Note 25)
tWSCLKl
–
167
ns
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (Note 25)
tLAG
–
50
167
ns
SI to Falling Edge of SCLK (Required Setup Time) (Note 26)
tSI(SU)
–
25
83
ns
Falling Edge of SCLK to SI (Required Setup Time) (Note 26)
tSI(HOLD)
–
25
83
ns
SO Rise Time
CL = 200 pF
tRSO
–
25
50
ns
SO Fall Time
CL = 200 pF
tFSO
–
25
50
ns
SI, CS, SCLK, Incoming Signal Rise Time (Note 26)
tRSI
–
50
ns
SI, CS, SCLK, Incoming Signal Fall Time (Note 26)
tRSI
–
50
ns
Time from Falling Edge of CS to SO Low Impedance (Note 27)
tSO(EN)
–
145
ns
Time from Rising Edge of CS to SO High Impedance (Note 28)
tSO(DIS)
–
65
145
ns
Time from Rising Edge of SCLK to SO Data Valid (Note 29)
0.2 VDD ≤ SO ≥ 0.8 VDD, CL = 200 pF
tVALID
–
65
105
ns
Notes
24.
RST
low duration measured with outputs enabled and going to OFF or disabled condition.
25.
Maximum setup time required for the 33984 is the minimum guaranteed time needed from the microcontroller.
26.
Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
27.
Time required for output status data to be available for use at SO. 1.0 k
on pullup on CS.
28.
Time required for output status data to be terminated at SO. 1.0 k
on pullup on CS.
29.
Time required to obtain valid data out from SO following the rise of SCLK.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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| MC33989DW | 功能描述:CAN 接口集成電路 SBC HIGH SPEED RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube |
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