![](http://datasheet.mmic.net.cn/200000/MC33984PNA_datasheet_15082278/MC33984PNA_15.png)
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33984
15
SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 33984 is a dual self-protected 4.0 m
silicon switch
used to replace electromechanical relays, fuses, and discrete
devices in power management applications. The 33984 is
designed for harsh environments, and it includes self-recovery
features. The device is suitable for loads with high inrush
current, as well as motors and all types of resistive and
inductive loads.
Programming, control, and diagnostics are implemented via
the Serial Peripheral Interface (SPI). A dedicated parallel input
is available for alternate and Pulse Width Modulation (PWM)
control of each output. SPI-programmable fault trip thresholds
allow the device to be adjusted for optimal performance in the
application.
The 33984 is packaged in a power-enhanced 12 x 12
nonleaded PQFN package with exposed tabs.
FUNCTIONAL DESCRIPTION
SPI Protocol Description
The SPI interface has a full duplex, three-wire synchronous
data transfer with four I/O lines associated with it: Serial Clock
(SCLK), Serial Input (SI), Serial Output (SO), and Chip Select
(CS).
The SI/SO terminals of the 33984 follow a first-in first-out
(D7/D0) protocol with both input and output words transferring
the most significant bit (MSB) first. All inputs are compatible
with 5.0 V CMOS logic levels.
The SPI lines perform the following functions:
Serial Clock (SCLK)
Serial clocks (SCLK) the internal shift registers of the 33984
device. The serial input (SI) terminal accepts data into the input
shift register on the falling edge of the SCLK signal while the
serial output (SO) terminal shifts data information out of the SO
line driver on the rising edge of the SCLK signal. It is important
that the SCLK terminal be in a logic low state whenever CS
makes any transition. For this reason, it is recommended that
the SCLK terminal be in a logic [0] state whenever the device is
not accessed (CS logic [1] state). SCLK has an active internal
pulldown, IDWN. When CS is logic [1], signals at the SCLK and
SI terminals are ignored and SO is tri-stated (high impedance).
Serial Input (SI)
This is a serial interface (SI) command data input terminal. SI
instruction is read on the falling edge of SCLK. An 8-bit stream
of serial data is required on the SI terminal, starting with D7 to
D0. The internal registers of the 33984 are configured and
controlled using a 4-bit addressing scheme, as shown in
internal pulldown, IDWN.
Serial Output (SO)
The SO data terminal is a tri-stateable output from the shift
register. The SO terminal remains in a high impedance state
until the CS terminal is put into a logic [0] state. The SO data is
capable of reporting the status of the output, the device
configuration, and the state of the key inputs. The SO terminal
changes states on the rising edge of SCLK and reads out on the
falling edge of SCLK. Fault and Input Status descriptions are
Chip Select (CS)
The CS terminal enables communication with the master
microcontroller (MCU). When this terminal is in a logic [0] state,
the device is capable of transferring information to, and
receiving information from, the MCU. The 33984 device latches
in data from the Input shift registers to the addressed registers
on the rising edge of CS. The device transfers status
information from the power output to the shift register on the
falling edge of CS. The SO output driver is enabled when CS is
logic [0]. CS should transition from a logic [1] to a logic [0] state
only when SCLK is a logic [0]. CS has an active internal pullup,
IUP.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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