參數(shù)資料
型號: MC33882
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: Six-Output Low-Side Switch with SPI and Parallel Input Control(帶SPI和并口輸入控制的6輸出低端開關)
中文描述: 六輸出低壓側(cè)開關SPI和并行輸入控制(帶的SPI和并口輸入控制的6輸出低端開關)
文件頁數(shù): 19/24頁
文件大小: 779K
代理商: MC33882
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33882
19
MODE
Operation
During normal operation output channels are controlled by
either the Serial Input control bits or the parallel input terminals.
If the
MODE
terminal is pulled high:
Serial input control is disabled.
Parallel input terminals IN0 to IN5 are ignored.
The SO terminal is tri-stated.
OUT0 and OUT1, OUT2 and OUT3, and OUT4 and OUT5
are controlled by the IN0 & IN1, IN2 & IN3, and IN4 & IN5
terminals, respectively. When a 10 k
pull-up resistor is used,
a logic high on the
MODE
terminal or an open serial output
terminal is flagged by the SPI when all bits are returned as
logic [1]s.
Although a logic high on the
MODE
terminal disables serial
control of outputs, data can still be clocked into the serial input
register. This allows programming of a desired state for the
outputs taking effect only when the
MODE
terminal returns to a
logic low. For applications using the SO terminal, daisy chaining
is permitted, but if the
MODE
terminal is high, writing to other
than the first IC in a daisy chain is not possible because the
serial outputs are tri-stated.
Output Drivers
The high-power OUT0 to OUT5 outputs are active clamped,
low-side switches driving 1.0 A typical or less loads. The low-
power OUT6 and OUT7 outputs are unclamped low-side
switches driving 30 mA typical or less loads. All outputs are
individually protected from short circuit or short-to-battery
conditions and transient voltages. The outputs are also
protected by short circuit device shutdown. Each output
individually detects and reports open load/short-to-ground and
short circuit/short-to-battery faults.
Fault Sense/Protection Circuitry
Each output channel individually detects shorted loads/
short-to-battery while the output is ON and open load/short-to-
ground while the output is OFF. OUT0 to OUT5 may also be
programmed via SPI bits 6 and 7 to detect open loads and
shorts-to-ground while the output is ON. Whenever a short or
open fault condition is present on a particular output channel, its
fault bit in the internal fault register indicates the fault with a
logic [1].
When a fault ends, its fault bit remains set until the SPI
register is read, then it returns to a logic [0], indicating a normal
condition. When the
CS
terminal is pulled low for serial
communication, the fault bits in the internal fault register latch,
preventing erroneous status transmissions and the forthcoming
communication reports this latched fault status. The SO
terminal serial output data for 8-bit SPI mode are the fault status
register bits.
For 16-bit SPI mode and SO terminal (non-daisy chained)
use, a transmitted double command provides the fault byte
followed by the first byte of the double command, becoming a
command verification. The status is sent back to the IC for fault
monitoring. Diagnostic interpretation of the following fault types
can be accomplished using the procedure described in the
paragraph entitled
Extensive Fault Diagnostics
, page 20:
Communication error
Open load/short-to-ground
Short-to-battery or short circuit
When serial communication is ended, the
CS
terminal
returns high, opening the fault status register to new fault
information and tri-stating the SO terminal.
Two fault conditions initiate protective action by the device:
A short circuit or short-to-battery on a particular output will
cause that output to go into a low duty cycle operation until
the fault condition is removed or the input to that channel
turns OFF.
A short circuit condition causes all channels to shut down,
ignoring serial and parallel inputs to the device.
To be detected and reported as a fault, a fault condition must
last a specified time (fault sense time or fault mask time). This
prevents any normal switching transients from causing
inadvertent fault status indications.
Fault status information should be ignored for V
BAT
levels
outside the 9.0 V to 17 V range. The fault reporting may appear
to function properly but may not be 100 percent reliable.
Short Circuit/Short-to-Battery Sensing and
Protection
When an output is turned ON, if the drain current limit is
reached, the current remains at the limit until the short circuit
sense time, t
SS
, has elapsed. At this time, the affected output
will shut down and its fault status bit switches to a logic [1]. The
output goes into a low duty cycle operation as long as the short
circuit condition exists and the input to that channel is ON.
This duty cycle is defined by the sense and refresh times. If
a short occurs after the output is ON, the fault sense time
indicates the fault and enters the low duty cycle mode at much
less than t
SS
. The duty cycle is low enough to keep the driver
from exceeding its thermal capabilities. When the short is
removed, the driver resumes normal operation at the next retry,
but the fault status bit does not return to a normal logic [0] state
until it is read from the SPI. When the
CS
terminal of this device
is pulled low, the fault status bits are latched, after which any
new fault information is not a part of this serial communication
event.
The low duty cycle operation for a short circuit condition is
required to protect the output. It is possible to override this duty
cycle if the input signal (parallel or SPI) turns the channel ON
and OFF faster than 10 kHz. For this reason control signals
should not exceed this frequency.
F
Freescale Semiconductor, Inc.
Go to: www.freescale.com
n
.
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