參數(shù)資料
型號(hào)： MC33689DWBR2
廠商： Motorola, Inc.
英文描述： System Basis Chip with LIN transceiver
中文描述： 系統(tǒng)基礎(chǔ)芯片收發(fā)器和LIN
文件頁(yè)數(shù)： 8/18頁(yè)
文件大?。?/td> 229K
代理商： MC33689DWBR2
MC33689
16
MC33689
6
SPI INTERFACE AND REGISTER DESCRIPTION
6.1
Data format description
The SPI is an 8 bits SPI. All bits are data bytes. The MSB is send first. The minimum time between two rising edges on the
CSB pin is 15us.
During an SPI communication the state of MISO reports the state of the SBC, at time of CSB high to low transitions. The status
flag are latched at CSB high to low transitions.
Following tables describe the SPI register bit meaning, “reset value” and “bit reset condition”.
Note 1: The first SPI read, after reset, returns the BATFAIL flag state on bit D4.
D7 signals INT source. After INT occur, D7 read as a “1” means other bits report the INT source. D7 read as a “0” mean no INT
occurred and other bit report real time status.
6.2
Write control bits:
6.2.1
Mode control bits:
6.2.2
High side switches control bits:
6.2.3
LIN pull up termination control bits:
D7
D6
D5
D4
D3
D2
D1
D0
W
LINSL2
LINSL1
LIN-PU
HS3
HS2
HS1
Mode2
Mode1
R
INT
source
LINWU
or
LINFAIL
VSOV
VSUV
BATFAIL
(note1)
VddT
HSst
L2
L1
Write Reset
value
00
0
-
Write Reset
condition
POR,
RESET
POR,
RESET
POR
POR,
RESET
POR,
RESET
POR,
RESET
Mode 2
Mode 1
Description
0
Sleep mode
01
Stop mode
1
0
Normal mode + W/D clear
1
Normal mode
HS1
Description
HS2
Description
HS3
Description
0
HS1 off
0
HS2 off
0
HS3 off
1
HS1 on (if IN = 1)
1
HS2 on (if IN = 1)
1
HS3 on
LIN-PU
Description
0
30k pull up connected in sleep and stop mode
1
30k pull up disconnected in sleep and stop mode
MOSI
MISO
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
D0
D1
D2
D3
D4
D5
D6
D7
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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