參數(shù)資料
型號(hào)： MC33689DWBR2
廠商： Motorola, Inc.
英文描述： System Basis Chip with LIN transceiver
中文描述： 系統(tǒng)基礎(chǔ)芯片收發(fā)器和LIN
文件頁(yè)數(shù)： 13/18頁(yè)
文件大小： 229K
代理商： MC33689DWBR2
MC33689
4
MC33689
2
ELECTRICAL CHARACTERISTICS
(Vs1 and Vs2 from 5.5V to 18V and Tamb from -40°C to 125°C unless otherwise noted)
Description
Symbol
Characteristics
Unit
Conditions
Min
Typ
Max
Vs1 and Vs2 pins (Device power supply)
Nominal DC Voltage range
Vsup
5.5
18
V
Input Voltage during Load Dump
VsupLD
40
V
Load dump situation
Input Voltage during jump start
VsupJS
27
V
Jump start situation (note 1)
Supply Current in Normal Mode (note 2)
Isup(norm)
5
7.5
mA
Iout at Vdd =10mA, LIN
recessive state
Supply Current in Sleep Mode (note 2)
Isleep
30
40
uA
Vdd off, Vsup<=13.5V
Supply Current in Stop Mode (note 2)
Istop
60
75
uA
Vdd ON with Iout<100uA,
Vsup<=13.5V
Supply voltage fall early warning thresh-
old
VSUVew
5.7
6
6.6
V
Normal mode, INT gener-
ated, bit VSUV set
VSUV flag hysteresis
VSUVhyst
1
V
guaranteed by design
Supply voltage over voltage warning
threshold
VSOVw
18
19.25
20.50
V
Normal mode, INT gener-
ated, bit VSOV set
VSOV flag hysteresis
VSOVhyst
220
mV
guaranteed by design
note 1: Device is fully functional. All functions are operating. Over temperature may occur.
note 2: Total current (IVs1+IVs2) measured at gnd pins.
Vdd (external 5V output for MCU supply). Specification with external capacitor 2uF<C<10uF and 200mOhms<=ESR<=1O ohm.
Normal mode. Capacitor value up to 47uF chemical can be used.
Vdd Output Voltage
Vddout
4.75
5
5.25
V
Idd from 2 to 50mA
5.5V< Vsup <27V
Dropout Voltage (note 1)
Vdddrop
100
200
mV
Idd = 50mA (note 1)
Vsup > 4.5V
Idd output current limitation (note 2)
Idd
50
110
200
mA
Internally limited
Over temperature pre warning (junction)
Tpre
120
135
160
°C
Normal mode, INT gener-
ated, Bit VddT set
guaranteed by design
Thermal Shutdown (junction)
Tsd
155
170
°C
Normal mode
guaranteed by design
Temperature threshold difference
20
30
45
°C
Normal mode (Tsd-Tpre)
guaranteed by design
Vsup range for Reset Active
Vsupr
3.5
V
0.5<Vdd<Vdd (Rst-th1)
Line Regulation
LR
20
150
mV
5.5V<Vsup<27V, Idd=10mA
Load Regulation
LD
40
150
mV
1mA<IIdd<50mA
note 1: measured when voltage has dropped 100mV below its nominal value.
note 2: total Vdd regulator current. A 5mA current for operational amplifier operation is included. Digital output supplied from Vdd.
Vdd: in Stop mode
Vdd Output Voltage (note 1)
Vddstop
4.75
5,00
5.25
V
Idd<=2mA
Idd current capability (note 2)
Idds
4
8
14
mA
Stop mode
Line regulation
LR-s
10
100
mV
5.5V<Vsup<27V, Idd=2mA
Load regulation
LD-s
40
150
mV
1mA<IIdd<5mA
note 1: when switching from Normal mode to Stop mode, or from Stop mode to Normal mode the output voltage can varies within the output
voltage specification.
note 2: when Idd is above Idds device enters reset mode
Reset: normal and stop modes (output pin only)
Reset threshold
Rst-th1
4.50
4.68
Vdd-0.2
V
High Level Output current
Ioh
-250
AV
out>0.7Vdd
Low Level Output Voltage (I0=1.5mA)
Vol
0
0.9
V
4.5V<Vsup<27V
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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