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參數(shù)資料
| 型號： | MC33121 |
| 廠商： | Motorola, Inc. |
| 英文描述： | LOW VOLTAGE SUBSCRIBER LOOP INTERFACE CIRCUIT |
| 中文描述： | 低電壓用戶環(huán)路接口電路 |
| 文件頁數(shù)： | 22/32頁 |
| 文件大?。?/td> | 570K |
| 代理商： | MC33121 |
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MC33121
22
MOTOROLA
A simultaneous occurrence of conditions a) and c) is not
detected as a fault. See Figures 12 to 15 for the threshold
variation with RL and VEE. Resetting of the fault detection cir-
cuit requires that the leakage resistance be increased to a
value between 10 k
and 20 k
, depending on VEE, RL, and
RS. Both ST1 and ST2 should be monitored for hookswitch
status to preclude not detecting a fault condition.
Figure 15 indicates the variation in fault thresholds for Tip–
to–VCC and Ring–to–Battery faults, and is valid only for loop
resistances of 200
to 800
. On loops larger than 800
,
the MC33121 does not reliably indicate the fault condition at
ST1 and ST2, but may indicate on–hook status instead. This
does not apply to Tip–to–Battery and Ring–to–VCC faults
which are correctly detected for lines beyond 800
.
e) PDI Input
The ST2 output can also be used as an input (PDI Input) to
power down the circuit, denying loop current to the subscrib-
er (by shutting off the external pass transistors), regardless
of the hookswitch position. Powering down is accomplished
by pulling PDI to a logic low with an open collector output, or
an NPN transistor as shown in Figure 30. The switching
threshold is
1.5 V. The current out of PDI, when pulled low,
is
800
μ
A. Releasing PDI allows the MC33121 to resume
normal operation.
If the external telephone is off–hook while the MC33121 is
powered down, sense currents at CP and TSI will result in
some loop current flowing through the loop and back into CN
and RSI. This current is generally on the order of 1.0 to
3.0 mA, determined primarily by the RS resistors, loop resis-
tance, and VEE. ST1 will continue to indicate the telephone’s
actual hook status while PDI is held low. The on–to–off hook
threshold is the same as that during normal operation, but
the off–to–on hook threshold is > 250 k
.
When powered down with the PDI pin, the receive gain
(VRXI to Tip/Ring) is muted by > 90 dB, and the transmit gain
(Tip/Ring to TXO) is muted by > 30 dB.
Power Dissipation, Calculation and Considerations
a) Reliability
The maximum power dissipated by the MC33121 must be
considered, and managed, so as to not exceed the junction
temperature listed in the Maximum Ratings Table. Exceeding
this temperature on a recurring basis will reduce long term
reliability, and possibly degrade performance. The junction
temperature also affects the statistical lifetime of the device,
due to long term thermal effects within the package. Today’s
plastic integrated circuit packages are as reliable as ceramic
packages under most environmental conditions. However,
when the ultimate in system reliability is required, thermal
managements must be considered as a prime system design
goal.
Modern plastic package assembly technology utilizes gold
wire bonded to aluminum bonding pads throughout the elec-
tronics industry. When exposed to high temperatures for pro-
tracted periods of time an intermetallic compound can form in
the bond area resulting in high impedance contacts and
degradation of device performance. Since the formation of
intermetallic compounds is directly related to device junction
temperature, it is incumbent on the designer to determine
that the device junction temperature is consistent with sys-
tem reliability goals.
Based on the results of almost ten years of + 125
°
C oper-
ating life testing, Table 2 has been derived indicating the rela-
tionship between junction temperature and time to 0.1% wire
bond failure.
Table 2. Statistical Lifetime
Junction
Temperature (
°
C)
Time
(Hours)
Time
(Years)
80
90
100
110
120
130
140
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
117.8
47.9
20.4
9.4
4.2
2.0
1.0
Motorola MECL Device Data, DL122
The “Time” in Table 2 refers to the time the device is operat-
ing at that junction temperature. Since the MC33121 is at a
low power condition (nominally 40 mW) when on–hook, the
duty cycle must be considered. For example, if a statistical
duty cycle of 20% off–hook time is used, operation at 130
°
C
junction temperature (when off–hook) would result in a statis-
tical lifetime of
10 years.
b) Power and Junction Temperature Calculation
The power within the IC is calculated by subtracting the
power dissipated in the two–wire side (the transistors and the
load) from the power delivered to the IC by the power sup-
plies. Refer to Figure 4 and 27.
PD = |VDD
IDD| + |VEE
IEE| – (IL
|VEP – VEN|)
The terms VEP and VEN are the DC voltages, with respect
to ground, at the EP and EN pins. These voltages can be
measured, or can be approximated by:
(20)
VEP
|VEE| + 2.1 V + (IL
35
)
– (30
IL)
VEN
Refer to Figure 23. The junction temperature is then calcu-
lated from:
TJ = TA + (PD
θ
JA)
where TA is the ambient air temperature at the IC package,
and
θ
JA is the junction–to–ambient thermal resistance
shown in Figure 39. The highest junction temperature will
occur at maximum VEE and VDD, maximum loop current,
and maximum ambient temperature.
If the above calculations indicate the junction temperature
will exceed the maximum specified, then it is necessary to
reduce the maximum loop current, ambient temperature,
and/or VEE supply voltage. Air flow should not be restricted
near the IC by tall components or other objects since even a
small amount of air flow can substantially reduce junction
temperature. For example, typically an air flow of 300 LFPM
(3.5 mph) can reduce the effective
θ
JA by 14 to 20% from
that which occurs in still air. Additionally, providing as much
copper area as possible at the IC pins will assist in drawing
away heat from within the IC package. For additional in-
formation on this subject, refer to the “Thermal Consider-
ations” section of Motorola MECL System Design Handbook,
and the “System Design Considerations” section of Motorola
MECL Device Data.
(21)
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