參數(shù)資料
型號： MC145572AFN
廠商： Freescale Semiconductor
文件頁數(shù)： 19/52頁
文件大?。?/td> 0K
描述： IC TRANSCEIVER ISDN 44-PLCC
標準包裝： 26
類型： 收發(fā)器
規(guī)程： RS232
電源電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 44-PLCC（17.525x17.525）
包裝： 管件
27
MC145572EVK
Note that the M and the A bits used in the IDL interface of the MC145574 S/T-Interface Transceiver are
not used by the MC145572, and, therefore, are not driven by the MC145572.
NTFSR: (NT U-Interface Transceiver Pin FSR).
This pin is an input when the MC145572 is congured for slave mode and an output when congured for
master mode, as established by switch S4-1, MAS/SLV. In the master mode this output is phase locked
to the signal received at the NT1 U-Interface. This signal is associated with data output from the Dout pin
of the MC145572. This signal is also connected to the FSC/FSR pin of the MC145574 S/T-Transceiver.
NTFSX: (NT U-Interface Transceiver Pin FSX).
This pin is an input when the MC145572 is congured for slave mode and an output when congured for
master mode, as established by switch S2-1, MAS/SLV. In the master mode this output is phase locked
to the signal received at the NT1 U-Interface. This signal is associated with data input to the Din pin of the
MC145572.
STIRQ: Interrupt Request T (S/T-Interface Transceiver IRQ).
The STIRQ pin is an active low open drain output used to signal the MCU devices that an interrupt condition
exists in the MC145574 S/T-Interface Transceiver. On clearing the interrupt condition, the STIRQ pin is
returned to the high impedance state.
NTSFAX: Transmit Superframe Alignment.
This pin carries a signal that indicates the rst 2B+D frame in a U superframe to be transmitted onto the
U-Interface.This signal is not active when the NT side MC145572 is congured for full GCI mode operation.
NTSFAR: Receive Superframe Alignment.
This pin carries a signal that indicates the rst 2B+D frame in a U superframe to be received from the
U-Interface.This signal is not active when the NT side MC145572 is congured for full GCI mode operation.
NTFREF: Synchronized Clock Out, MCU Mode.
When the NT side MC145572 is congured for MCU mode operation, S4-4 in IDL2 position, this pin
provides the recovered timing clock. The frequency of the clock at this pin is selected by programming the
NT side MC145572 registers BR7(b4) and OR7(b4).
NTFREFO: Synchronized Clock Out, GCI Mode.
When the NT side MC145572 is congured for full GCI mode operation, S4-4 in GCI position, this pin
provides the recovered timing clock. The frequency of the clock is selected between 2.048 MHz and
512 kHz by the setting of S3-4, GCI2048/GCI512.
NTCLK or NTGTCLK: Gated IDL Clock Output.
This pin provides a gated clock output. The clock input of an external bit error rate tester should be
connected to this signal.
GND: Ground.
Negative Power Supply.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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