參數(shù)資料
型號： MC145572AFN
廠商： Freescale Semiconductor
文件頁數(shù)： 15/52頁
文件大小： 0K
描述： IC TRANSCEIVER ISDN 44-PLCC
標準包裝： 26
類型： 收發(fā)器
規(guī)程： RS232
電源電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 44-PLCC（17.525x17.525）
包裝： 管件
23
MC145572EVK
C: Other S/T-Interface Transceiver Loop-Backs.
A variety of S/T-Interface and IDL loop-backs may be initiated from the command line interface by setting
BR6(b7 b0) in the S/T-Interface Transceiver. Refer to the MC145574/75 S/T-Interface data sheet for more
information.
D: IDL Loop-Back Internal to NT U-Interface Transceiver Towards NT1 Side.
This loop-back is also implemented via the command line interface by setting BR6(b3) and/or BR6(b2)
and/or BR6(b1) in the NT U-Interface Transceiver to 1. Refer to the MC145572 U-Interface Transceiver
data sheet for more information.
E: NT U-Interface Transceiver Analog Loop-Backs Toward NT1 Side.
From command line interface, invoke LPU N D. See also the Loop-Back Modes section in the MC145572
U-Interface Transceiver data sheet.
F: IDL Loop-Back Internal to U-Interface Transceiver Towards U-Interface.
From LT activation menu, select option B. From the command line interface for either the LT or NT1 side,
this loop-back is implemented by setting BR6(b7) and/or BR6(b6) and/or BR6(b5) to 1.
G: LT U-Interface Transceiver Analog Loop-Backs Toward LT Side.
From command line interface, invoke LPU L D. See also the Loop-Back Modes section in the MC145572
U-Interface Transceiver data sheet.
H: IDL Loop-Back Internal to LT U-Interface Transceiver Towards Connector JP9.
This loop-back is implemented from the command line interface by setting BR6(b3) and/or BR6(b2) and/or
BR6(b1) in the LT side U-Interface Transceiver to 1.
I: External Hardware IDL Loop-Back on LT Side.
Place a jumper between BNC J7 LTRXDATA and BNC J8 LTXDATA. Then from the LT/NT activation menu,
select option E or I.
2.6
MC145572EVK TEST HEADERS
There are four headers on the MC145572EVK with signals of signicant interest to the user.
J22 Makes available key signals on the NT side such as the IDL, SCP, and bit error rate test interfaces.
J11 and J17 Makes available key test signals from the NT side U-Interface Transceiver.
J1 and J6 Makes available key test signals from the LT side U-Interface Transceiver.
J9 Makes available key signals on the LT side such as the IDL, SCP, and bit error rate test interface.
J1 and J11, 2 x 8 headers, make important MC145572 U-Interface Transceiver test signals easily
accessible. Pins 2, 4, 6, and 10 can be decoded to generate an eye pattern. Also, an external cable can
be connected to these headers if it is desired to operate the corresponding U-Interface Transceiver from
a parallel data port. Refer to the MC145572 data sheet for the eye data application circuit and timing
diagram.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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