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參數(shù)資料
| 型號： | MC145152DW2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 24/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PAR-IN PLL FREQ SYNTH 28-SOIC |
| 標(biāo)準包裝： | 26 |
| 類型： | PLL 時鐘/頻率合成器 |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 25MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 9 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 管件 |
MC145152-2 Parallel-Input (Interfaces with Dual-Modulus Prescalers)
MC145151-2 and MC145152-2 Technical Data, Rev. 5
Freescale Semiconductor
9
N0 - N9
N Counter Programming Inputs (Pins 11 - 20)
The N inputs provide the data that is preset into the
÷ N counter when it reaches the count of 0. N0 is the
least significant digit and N9 is the most significant. Pull-up resistors ensure that inputs left open remain
at a logic 1 and require only a SPST switch to alter data to the zero state.
A0 - A5
A Counter Programming Inputs
(Pins 23, 21, 22, 24, 25, 10)
The A inputs define the number of clock cycles of fin that require a logic 0 on the MC output (see
Section 4.3, “Dual-Modulus Prescaling,” on page 21). The A inputs all have internal pull-up resistors that
ensure that inputs left open will remain at a logic 1.
OSCin, OSCout
Reference Oscillator Input/Output (Pins 27, 26)
These pins form an on-chip reference oscillator when connected to terminals of an external parallel
resonant crystal. Frequency setting capacitors of appropriate value must be connected from OSCin to
ground and OSCout to ground. OSCin may also serve as the input for an externally-generated reference
signal. This signal is typically ac coupled to OSCin, but for larger amplitude signals (standard CMOS logic
levels) dc coupling may also be used. In the external reference mode, no connection is required to OSCout.
2.2.2
Output Pins
φ
R, φV
Phase Detector B Outputs (Pins 7, 8)
These phase detector outputs can be combined externally for a loop-error signal.
If the frequency fV is greater than fR or if the phase of fV is leading, then error information is provided by
φ
V pulsing low. φR remains essentially high.
If the frequency fV is less than fR or if the phase of fV is lagging, then error information is provided by φR
pulsing low.
φ
V remains essentially high.
If the frequency of fV = fR and both are in phase, then both φV and φR remain high except for a small
minimum time period when both pulse low in phase.
MC
Dual-Modulus Prescale Control Output (Pin 9)
Signal generated by the on-chip control logic circuitry for controlling an external dual-modulus prescaler.
The MC level will be low at the beginning of a count cycle and will remain low until the
÷ A counter has
counted down from its programmed value. At this time, MC goes high and remains high until the
÷ N
counter has counted the rest of the way down from its programmed value (N - A additional counts since
both
÷ N and ÷ A are counting down during the first portion of the cycle). MC is then set back low, the
counters preset to their respective programmed values, and the above sequence repeated. This provides for
a total programmable divide value (NT)= NP+A where P and P + 1 represent the dual-modulus prescaler
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| MC145152DW2R2 | 功能描述:IC PAR-IN PLL FREQ SYNTH 28-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MC145155P | 制造商:Motorola Inc 功能描述: |
| MC145158-2 | 制造商:Motorola Inc 功能描述: |
| MC145158DW2 | 功能描述:IC SER-IN PLL FREQ SYNTH 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MC145158DW2R2 | 制造商: 功能描述: 制造商:undefined 功能描述: |
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