參數(shù)資料
型號(hào): MC145152DW2
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 2/24頁(yè)
文件大?。?/td> 0K
描述: IC PAR-IN PLL FREQ SYNTH 28-SOIC
標(biāo)準(zhǔn)包裝: 26
類型: PLL 時(shí)鐘/頻率合成器
PLL:
輸入: 時(shí)鐘
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 無(wú)/無(wú)
頻率 - 最大: 25MHz
除法器/乘法器: 是/無(wú)
電源電壓: 3 V ~ 9 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 28-SOIC W
包裝: 管件
MC145151-2 and MC145152-2 Technical Data, Rev. 5
10
Freescale Semiconductor
MC145152-2 Parallel-Input (Interfaces with Dual-Modulus Prescalers)
divide values respectively for high and low MC levels, N the number programmed into the
÷ N counter,
and A the number programmed into the
÷ A counter.
LD
Lock Detector Output (Pin 28)
Essentially a high level when loop is locked (fR, fV of same phase and frequency). Pulses low when loop
is out of lock.
2.2.3
Power Supply
VDD
Positive Power Supply (Pin 3)
The positive power supply potential. This pin may range from + 3 to + 9 V with respect to VSS.
VSS
Negative Power Supply (Pin 2)
The most negative supply potential. This pin is usually ground.
2.3
Typical Applications
Figure 7. Synthesizer for Land Mobile Radio VHF Bands
NOTES:
1. Off-chip oscillator optional.
2. The
φ
R and φV outputs are fed to an external combiner/loop filter. See the Phase-Locked Loop - Low-Pass Filter Design page
for additional information. The
φ
R and φV outputs swing rail-to-rail. Therefore, the user should be careful not to exceed the com-
mon mode input range of the op amp used in the combiner/loop filter.
LOCK DETECT SIGNAL
10.24 MHz
NOTE 1
R1
NOTE 2
+
150 - 175 MHz
5 kHz STEPS
÷ 64/65 PRESCALER
MC145152-2
MC
LD
A0
A5
N9
OSCin
VDD
VSS
OSCout
RA2
RA1
φ
R
φ
V
fin
-
VCO
RA0
N0
+ V
R1
R2
C
R2
C
“1"
NO CONNECTS
CHANNEL PROGRAMMING
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