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參數(shù)資料
| 型號： | MC13760VFR2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DIGITAL CELL REC 104-BGA |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | 多協(xié)議 |
| 電源電壓： | 2.775V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 104-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 104-BGA（10x10） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | Q1146713 |
MC13760
5
MOTOROLA RF PRODUCTS DEVICE DATA
Table 1. BGA Contact Identification (continued)
SIGNAL TYPE
DESCRIPTION
BALL NAME
BALL #
J6
VCNTO
TDMA RFPA gain control voltage output.
Analog Output
J7
OSCVCC
Supply for the crystal oscillator.
Supply 2.775 V
J8
XTALWARP
Output of the 9 bit WARP D/A to be used for compensation/correction of the
reference crystal frequency.
Analog Output
J9
OSCENB
Digital input used to control the crystal oscillator circuit. A logic low selects the
internal oscillator. Integrated weak pulldown.
Digital Input
J10
RXCLK/test_so3
SSI RX clock in GSM mode; not used in TDMA mode.
Or scan data output for transmit power amp control module.
Digital Output
J11
SRD/test_so6
SSI receive data. Or scan data output for Adapt Generator module.
Digital Output
K1
VCOCT1
Low current output of the 6 bit main RX VCO Coarse Tune D/A.
Analog Output
K2
MNCPGND
Ground for the main phase detector and charge pump.
Ground
K3
SFGND
Ground for the super filter.
Ground
K4
SFBYP
Bypass capacitor for the super filter. (1.0 f)
Analog
K5
OSCGND
Ground for the crystal oscillator.
Ground
K6
XTALBASE/sc_clk26
Crystal oscillator base. Or scan clock input for xtal clock zone.
RF Input
K7
LOGICVCC
Supply for the main synthesizer logic, adapt control and test MUXs.
Supply 2.775 V
K8
CEX
Digital input that latches in the SPI data. (Low Active)
Digital Input
K9
SPICLK
SPI clock input.
Digital Input
K10
STD/test_si3
SSI transmit data. Or scan data input for transmit.
Digital Input
K11
TXCLK/SCK/test_so5
Bit clock for TX data transfer in GSM mode. Bit clock for RX and TX data
transfer in TDMA mode. Or scan data output for reference clock Frac–N
accumulator module.
Digital Output
L1
ADAPT
Synthesizer output to adapt the loop filter for the main PLL.
Analog Output
L2
CPGT
Charge pump output for the main TX LO (GSM).
Analog Output
L3
CPGITR
Charge pump output for the main RX LO (GSM, TDMA TX and RX).
Analog Output
L4
SFOUT
Super filter output. (45 mA max) (bypass with 0.01 f)
Analog Output
L5
VBLIN
TDMA RFPA bias control voltage output.
Analog Output
L6
XTALEMIT
Crystal oscillator emitter.
RF Output
L7
LOGICGND
Ground for the main synthesizer logic, adapt control and test MUXs.
Ground
L8
SERIALGND
Ground for the SSI and SPI serial communication ports.
Ground
L9
SPII
SPI data input.
Digital Input
L10
DMCS/test_si2
Digital input that starts the GSM TX modulation.
Or scan data input for MODROM module.
Digital Input
L11
RXFS/SFS/test_so7
RX SSI frame sync in GSM mode; SSI frame sync in TDMA mode.
Or scan data output for 5 bit and 8 bit xtal clock dividers.
Digital Output
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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