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參數(shù)資料
| 型號(hào)： | MC13760VFR2 |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 3/6頁(yè) |
| 文件大小： | 0K |
| 描述： | IC DIGITAL CELL REC 104-BGA |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 1/1 |
| 規(guī)程： | 多協(xié)議 |
| 電源電壓： | 2.775V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 104-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 104-BGA（10x10） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | Q1146713 |
MC13760
3
MOTOROLA RF PRODUCTS DEVICE DATA
Table 1. BGA Contact Identification
BALL #
BALL NAME
DESCRIPTION
SIGNAL TYPE
A1
PRAGNDDIG
Ground for the preamp substrate.
Ground
A2
PRAGND
Ground for the preamp.
Ground
A3
PREINGB
GSM IF preamp input.
RF Input
A4
PREINIB
TDMA IF preamp input.
RF Input
A5
BBFGND
Ground for the baseband filters.
Ground
A6
DCLQCP
DC Offset Correction Loop (input) capacitor – Q channel
Analog Input
A7
CREF
Bypass capacitor for the bandgap regulator.
Analog
A8
OUTQ
TDMA Q channel analog transmit data.
Analog Output
A9
OUTIB
TDMA I channel analog transmit data.
Analog Output
A10
TSLOTB
TDMA low level transmit slot.
Analog Output
A11
TSLOT
TDMA low level transmit slot.
Analog Output
B1
RFA0
RF attenuator 0 control line. (This line is a driver for an external RF attenuator.)
Digital Output
B2
DMXGND
Ground for the mixer.
Ground
B3
PREING
GSM IF preamp input.
RF Input
B4
PREINI
TDMA IF preamp input.
RF Input
B5
PRAVCC2
Supply for the preamp output stage.
Supply 2.775 V
B6
DCLICP
DC Offset Correction Loop (input) capacitor – I channel
Analog Input
B7
GPO3/test_so2
SPI port expansion 3. Or scan data output for MODROM module.
Digital Output
B8
TCAPP
Differential reference capacitor.
Analog
B9
REFGND
Ground for the internal reference.
Ground
B10
REFVCC
Supply for the internal reference.
Supply 2.775 V
B11
TCLK
TDMA low level transmit clock.
Analog Output
C1
DMXVCC
Supply for the mixer.
Supply 2.775 V
C2
DMXGNDDIG
Ground for the mixer substrate and quadrature generator.
Ground
C3
PRAVCC1
Supply for the preamp.
Supply 2.775 V
C4
BBFVCC
Supply for the baseband filters.
Supply 2.775 V
C5
DCLICIN
DC Offset Correction Loop (output) capacitor – TDMA – I channel
Analog Output
C6
DCLQCIN
DC Offset Correction Loop (output) capacitor – TDMA – Q channel
Analog Output
C7
TCAPM
Differential reference capacitor.
Analog
C8
OUTQB
TDMA Q channel analog transmit data.
Analog Output
C9
CLKSEL
Selects the source for the clock output to the digital circuitry of the radio as
either the crystal reference/divided crystal reference or the Step Up
PLL/divided Step Up PLL. A low on this pin selects the crystal
reference/divided crystal reference. A high on this pin selects the Step Up
PLL/divided Step Up PLL. Integrated weak pulldown.
Digital Input
C10
TCLKB
TDMA low level transmit clock.
Analog Output
C11
QGND
Quiet analog ground for the PA D/A and the data processing circuits.
Ground
D1
LOIN
Input port for the second LO VCO signal.
RF Input
D2
DMXVCCDIG
Supply for the quadrature generator.
Supply 2.775 V
D3
TEST2/EERQ
Test input/MUX 2 output. (Various signals are buffered and MUX’d to this pin.
Output signal is determined by programming of test bits.) Or with EER active,
TDMA Q channel transmit data.
Analog Test Point
D4
TEST1/EERI
Test input/MUX 1 output. (Various signals are buffered and MUX’d to this pin.
Output signal is determined by programming of test bits.) Or with EER active,
TDMA I channel transmit data.
Analog Test Point
D6
PKGGND1
Ground for the package flag (no direct connection to die).
Pkg Ground
D8
OUTI
TDMA I channel analog transmit data.
Analog Output
D9
TESTD/GPO4
Digital test point. (Various digital signals are MUX’d to this pin. Output is
determined by programming of test bits.) Or SPI port expansion 4.
Digital Test Point
Digital Output
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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