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參數(shù)資料
| 型號： | MC13760VFR2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 4/6頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DIGITAL CELL REC 104-BGA |
| 標準包裝： | 1,500 |
| 類型： | 收發(fā)器 |
| 驅動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | 多協(xié)議 |
| 電源電壓： | 2.775V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 104-LFBGA |
| 供應商設備封裝： | 104-BGA（10x10） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | Q1146713 |
MC13760
4
MOTOROLA RF PRODUCTS DEVICE DATA
Table 1. BGA Contact Identification (continued)
SIGNAL TYPE
DESCRIPTION
BALL NAME
BALL #
D10
QVCC
Quiet analog supply for the PA D/A and the data processing circuits.
Supply 2.775 V
D11
NGND
Noisy analog ground for the VCO D/A, AOC D/A and the data processing
circuits.
Ground
E1
VAG
Analog ground.
Analog
E2
AGCGND
Ground for the AGC.
Ground
E3
VAGBYP
Bypass capacitor for the analog ground voltage.
Analog
E9
NVCC
Noisy analog supply for the VCO D/A, AOC D/A and the data processing
circuits.
Supply 2.775 V
E10
RSTB
Reset. Low true input. Integrated weak pullup.
Digital Input
E11
TM
Enable for the internal scan test.
Digital Input
F1
AGCVCC
Supply for the AGC.
Supply 2.775 V
F2
TXKEYOUT/test_so4
Conditioned TXKEY out.
Or scan data output for reference clock module.
Digital Output
F3
AGC
Capacitor for the TDMA AGC.
Analog
F4
PKGGND2
Ground for the package flag (no direct connection to die).
Pkg Ground
F8
PKGGND3
Ground for the package flag (no direct connection to die).
Pkg Ground
F9
PLLCPVCC
Supply for the Step Up PLL phase detector and charge pump.
Supply 5.0 V
F10
CLKOUT
Clock output to the digital circuitry of the radio. Ranges are 13.0 to 16.8 MHz, or
26.0 to 33.6 MHz. The actual frequency provided will depend upon the
configuration of the Step Up PLL and the SPI selected configuration of the
MC13760.
Analog Output
F11
PLLCP
Charge pump output for the Step Up PLL.
Analog Output
G1
PRSCIN
Main LO prescaler input.
RF Input
G2
MAINGND
Ground for the main prescaler and divider.
Ground
G3
AOCDRIVE
Output to the PA bias circuitry drive input. (Output drive impedance is 620
Ohms.)
Analog Output
G9
PLLEMIT
Emitter of the oscillator transistor for the Step Up PLL.
RF Output
G10
REFPLLVCC
Supply for the Step Up PLL VCO and dividers.
Supply 2.775 V
G11
PLLBASE/vco_clk
Base of the oscillator transistor for the Step Up PLL.
Or scan clock input for VCO clock zone.
RF Input
H1
SATDET/test_si4
Input indicating saturation.
Or scan data input for reference clock module.
Digital Input
H2
GPO2/test_so8
SPI port expansion 2. Or Main PLL Adapt Timer output. Or scan data output for
SSI module.
Digital Output
H3
MAINVCC
Supply for the main prescaler and divider.
Supply 2.775 V
H4
MNCPVCC
Supply for the main phase detector and charge pump.
Supply 5.0 V
H6
PKGGND4
Ground for the package flag (no direct connection to die).
Pkg Ground
H8
TXE/TXKEY/test_si8
Transmit slot enable in TDMA mode; digital input to start/stop the PA Control
sequence in GSM mode. Or scan data input for SSI module.
Digital Input
H9
RXACQ/test_si7
Serial bus enable.
Or scan data input for 5 bit and 8 bit xtal clock dividers.
Digital Input
H10
REFPLLGND
Ground for the Step Up PLL.
Ground
H11
SERIALVCC
Supply for the SSI and SPI serial communication ports.
Supply 1.8 — 2.775V
J1
GPO1/test_so1
SPI port expansion 1. Or Coarse Tune Adapt Timer output. Or scan data output
for main Frac–N.
Digital Output
J2
VCOCT2
High current (ADAPT) output of the 6 bit main RX VCO Coarse Tune D/A.
Analog Output
J3
DETSW/test_si1
Output to the PA control circuitry power range input (open drain).
Or scan data input for main Frac–N.
Analog Output
J4
SFVCC
Supply for the super filter.
Supply 2.775 V
J5
ASW/sc_inp1
TDMA antenna switch control input. Or scan data input for reference clock
Frac–N accumulator module.
Digital Input
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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