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參數(shù)資料
| 型號： | MC100SX1451FI100FI |
| 廠商： | Motorola, Inc. |
| 英文描述： | Current-Limited, Power-Distribution Switches 8-MSOP-PowerPAD -40 to 85 |
| 中文描述： | AUTOBAHNE⑩⑩SPANCEIVERE |
| 文件頁數(shù)： | 4/17頁 |
| 文件大?。?/td> | 197K |
| 代理商： | MC100SX1451FI100FI |
MC100SX1451FI100
MOTOROLA
ECLinPS and ECLinPS Lite
DL140 — Rev 3
4
read or write data from the chip is accomplished with the
input STRB signal , combined with the output FULL signal.
Transmit Register
The transmit register is a 32–bit wide parallel–loadable
register. This register interfaces to the bi–directional TTL
compatible data bus.
Access to this register is controlled via
the Register Read/Write Logic.
PISO Shift Register
The PISO (Parallel In/Serial Out) Register accepts data
from the Transmit Register and converts it into a serial bit
stream. This register is under control of the PISO Control
Logic. The shift register can be adjusted to handle 16–bit or
32–bit data traffic based on the state of the appropriate field
in the Control Register.
PISO Control Logic
The PISO (Parallel In/Serial Out) Control Logic is
responsible for controlling the transfer of data out from the
AutoBahn to the serial bus. This logic interfaces to the PISO
Shift Register and the SYNC Bit Generator. It is driven by the
PLL Clock Generator.
SYNC Bit Generator
This circuitry inserts one bit of timing information into the
data stream before every byte of data is sent to the Serial Bus
Transceiver and transmitted. This timing information is used
by the receiver to properly re–clock the incoming data
stream. To support the maximum data rate of 100 MByte/sec,
the actual serial shift rate is 900 MBit/s NRZ, rather than
800 MBit/s NRZ. The insertion and removal of SYNC bits is
transparent to the end user.
Serial Bus Transceiver
The transceiver implements a two signal bi–directional
differential bus. The transceiver circuitry consists of a highly
sensitive differential receiver and a cutoff driver. The receiver
accepts a differential signal from the serial bus. This
differential signal is amplified and limited by the receiver
before being routed to the clock generation circuitry for clock
extraction and data re–timing.
The cutoff driver is used to transmit serial data on to the
bus. The outputs switch between a normal HIGH level (VOH)
and a cutoff LOW signal – when low the output emitter
follower is turned ’off’, thus presenting a high impedance to
the bus. If the cutoff driver is disabled, both outputs of the
differential pair go to the cutoff state so the bus resource is
available for use by other AutoBahn chips sharing the
same bus.
Differential Detector
The differential detector is used to recognize when the
serial bus goes out of the cutoff state and into a differential
steady state condition. The differential detector is only
utilized at the very start of a transmission. The detector
informs the SIPO Control Logic that the serial bus is no
longer in cutoff so that the bus BUSY signal can be asserted
by the device.
PLL Clock Generator
The Clock Generator circuitry synthesizes a master timing
clock from the frequency reference signal (FOSC) input. The
clock generator provides timing signals used to support the
transfer rate of 900 MBit/s. The clock is generated by a
Phase Locked Loop (PLL) which requires a simple external
capacitor to set the loop filter bandwidth. The value for C1 is
2700 pF. This circuitry is used to provide the master timing for
the PISO and SIPO Control Logic blocks.
SYNC Bit Extractor
The SYNC Bit Extractor removes each SYNC bit from the
incoming data stream. It is controlled by the SIPO Control
Logic. If a SYNC bit is not detected at the proper bit time in
the extraction process, a field will be set in the Error Register
to indicate that a transmission error has occurred.
SIPO Shift Register
The SIPO (Serial In/Parallel Out) Register accepts data
from the SYNC Bit Extractor and converts it into a parallel
word that is then transferred to the Receive Register. The
operation of this shift register is controlled by the SIPO
Control Logic.
SIPO Control Logic
The SIPO (Serial In/Parallel Out) Control Logic is
responsible for controlling the transfer of data into the
AutoBahn. This circuitry performs all the critical control
functions to allow the AutoBahn to accept and process the
incoming serial data stream. The SIPO Control Logic has the
ability to detect certain transmission related errors and set
the appropriate field(s) in the Error Register.
Receive Register
The receive register is a 32–bit wide parallel load register.
It accepts data from the SIPO (Serial In/Parallel Out) Shift
Register. This register interfaces to the bi–directional TTL
compatible data bus.
Access to this register is controlled via
the Register Read/Write Logic.
Error Register
The AutoBahn has the capability to detect certain
transmission related error conditions. These errors are
detected by the SIPO Control Logic which sets the
appropriate error field in the Error Register. The register fields
are described in detail in the section containing the Control
and Error Register Bit Definition. The Error Register has
additional logic that is used to generate the ERROR signal.
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