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參數(shù)資料
| 型號： | MC100SX1451FI100FI |
| 廠商： | Motorola, Inc. |
| 英文描述： | Current-Limited, Power-Distribution Switches 8-MSOP-PowerPAD -40 to 85 |
| 中文描述： | AUTOBAHNE⑩⑩SPANCEIVERE |
| 文件頁數(shù)： | 3/17頁 |
| 文件大小： | 197K |
| 代理商： | MC100SX1451FI100FI |
MC100SX1451FI100
ECLinPS and ECLinPS Lite
DL140 — Rev 3
3
MOTOROLA
PIN DESCRIPTIONS
Name
I/O
Description
TTL COMPATIBLE I/O
RESET
I
Asynchronous reset signal which places the AutoBahn into default state. In most applications, RESET should
only have to be asserted on system startup.
R/W
I
Read/Write control signal. Used to select between writing to or reading from the AutoBahn.
REGSEL
I
Control signal used to select between the Parallel Data Register and the Control and Error Register(s). A logic
‘H’ selects the data register while a logic ‘L’ selects the Control and Error Register(s).
D00 – D31
I/O
Bi–directional data inputs/outputs. These pins comprise the data bus to be used to interface to the user host
interface. D00 is the least significant bit.
STRB
I
Data strobe signal. During a write, it indicates that data is valid on the parallel bus. While in a read, it indicates
that the AutoBahn can now place data on the parallel interface.
FULL
O
Signal which indicates that the transmitter or receiver presently contains data. In conjunction with the STRB
signal, it is used to implement a two signal handshake for parallel data transfers.
BUSY
O
Serial bus BUSY signal, used to indicate to the parallel interface that the AutoBahn bus is presently in use.
ERROR
O
Control output which is used to indicate that the AutoBahn has identified a fault condition. The error condition
can then be read out from the Error Register.
FOSC
I
25.00MHz clock source from a crystal oscillator reference.
PECL COMPATIBLE I/O
SER/SER
I/O
Differential serial data inputs/outputs which operate at modified PECL levels.
POWER, GROUND AND FILTER PINS
Name
Number
Description
C1
1
PLL Filter Capacitor Pin
VCCE
1
Positive Supply for Internal PECL Logic Circuitry
VCCO
1
Positive Supply for PECL Outputs
VEE
1
Ground for PECL
VCCT
7
Positive Supply for TTL Compatible Signals
VEET
8
Ground for TTL Compatible Signals
VCCX
1
Positive Supply for VCO
VEEX
1
Ground for VCO
BLOCK DIAGRAM FUNCTIONAL DESCRIPTION
Reset Logic
The Reset Logic generates the internal reset signal used
to set the device into a known state. The reset signal clears
the Control and Error Registers and resets the SIPO and
PISO Control Logic. The external reset signal is validated
with the FOSC input clock to assure that a valid reset pulse
has been applied to the chip. The external reset input pin
(RESET) must be low for a minimum of 125 nsec after the
FOSC input is stable. STRB assertion may occur no earlier
than 500 nsec after RESET deassertion (reset recovery
time).
Control Register
The Control Register is used to configure the operation of
the AutoBahn. The register fields are described in detail in
the section containing the Control and Error Register Bit
Definition.
Register Read/Write Control Logic
This logic is utilized to access the Transmit Register, the
Receive Register, and the Control and Error Registers from
the parallel bus. The interface protocol utilizes two direction
control signals (R/W and REGSEL). The actual handshake to
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