- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄26792 > MC100ES8111FA (FREESCALE SEMICONDUCTOR INC) 100E SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 PDF資料下載
參數(shù)資料
| 型號： | MC100ES8111FA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 100E SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026BBA, LQFP-32 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 344K |
| 代理商： | MC100ES8111FA |
Advanced Clock Drivers Devices
2
Freescale Semiconductor
MC100ES8111
Figure 1. MC100ES8111 Logic Diagram
Figure 2. 23-Lead Package Pinout (Top View)
0
1
CLK0
CLK1
CLK_SEL
VCC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
OE
Q8
VCCO
Q2
Q1
Q0
VCC0
Q7
Q9
Q3
Q4
Q5
Q6
V
CC
CL
K_
SE
L
CLK
0
CLK
0
OE
CLK
1
CLK
1
GN
D
25
26
27
28
29
30
31
32
15
14
13
12
11
10
9
12
3
4
56
7
8
24
23
22
21
20
19
18
17
16
MC100ES8111
VCCO
Q2
Q1
Q0
Q7
Q8
Q9
Table 1. Pin Configuration(1)
1. Input pull-up/pull-down resistors have a value of 75 k
.
Pin
I/O
Type
Function
CLK0, CLK0
Input
HSTL
Differential HSTL reference clock signal input
CLK1, CLK1
Input
PECL
Differential PECL reference clock signal input
CLK_SEL
Input
LVCMOS
Reference clock input select
OE
Input
LVCMOS
Output enable/disable. OE is synchronous to tlhe input reference clock which
eliminates possible output runt pulses when the OE state is changed.
Q[0-9], Q[0-9]
Output
HSTL
Differential clock outputs
GND
Supply
Negative power supply
VCC
Supply
Positive power supply of the device core (3.3 V)
VCCO
Supply
Positive power supply of the HSTL outputs. All VCCO pins must be connected to the
positive power supply (1.5 V or 1.8 V) for correct DC and AC operation.
Table 2. Function Table
Control
Default
0
1
CLK_SEL
0
CLK0, CLK0 (HSTL) is the active differential clock
input
CLK1, CLK1 (PECL) is the active differential clock
input
OE
0
Q[0-9], Q[0-9] are active. Deassertion of OE can be
asynchronous to the reference clock without
generation of output runt pulses.
Q[0-9] = L, Q[0-9] =H (outputs disabled). Assertion of
OE can be asynchronous to the reference clock
without generation of output runt pulses.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC100H640FNR2 | 100H SERIES, LOW SKEW CLOCK DRIVER, 6 TRUE OUTPUT(S), 2 INVERTED OUTPUT(S), PQCC28 |
| MC100H641FNR2 | 100H SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28 |
| MC100H644FNR2 | 100H SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 2 INVERTED OUTPUT(S), PQCC20 |
| MC100LVE111FNR2 | 100LVE SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 9 INVERTED OUTPUT(S), PQCC28 |
| MC100LVE111FN | 100LVE SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 9 INVERTED OUTPUT(S), PQCC28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100ES8111FAR2 | 制造商:Integrated Device Technology Inc 功能描述:CLOCK DRVR 2-IN HSTL 32LQFP - Tape and Reel |
| MC100H600FN | 功能描述:轉(zhuǎn)換 - 電壓電平 9-Bit TTL to ECL RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| MC100H600FNG | 功能描述:轉(zhuǎn)換 - 電壓電平 9-Bit TTL to ECL RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| MC100H600FNR2 | 功能描述:轉(zhuǎn)換 - 電壓電平 9-Bit TTL to ECL RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| MC100H600FNR2G | 功能描述:轉(zhuǎn)換 - 電壓電平 9-Bit TTL to ECL RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。