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參數(shù)資料
| 型號： | MC100EP446FAG |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | 3.3 V/5 V 8-Bit CMOS/ECL/TTL Data Input Parallel/Serial Converter |
| 中文描述： | 100E SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, PQFP32 |
| 封裝： | LEAD FREE, PLASTIC, LQFP-32 |
| 文件頁數(shù)： | 16/20頁 |
| 文件大小： | 278K |
| 代理商： | MC100EP446FAG |
MC10EP446, MC100EP446
http://onsemi.com
16
The differential synchronous CKEN inputs (Pins 6 and 7), disable the internal clock circuitry. The synchronous CKEN will
suspend all of the device activities and prevent runt pulses from being generated. The rising edge of CKEN followed by the
falling edge of CLK will suspend all activities. The falling edge of CKEN followed by the falling edge of CLK will resume
all activities (Figure 13).
Figure 13. Timing Diagram with CKEN with CKSEL HIGH
CLK
CKEN
SOUT
CKSEL
D1
1
D0
1
D2
1
D3
1
PCLK
D4
1
D5
1
Internal Clock
Disabled
Internal Clock
Enabled
The differential PCLK output (Pins 14 and 15) is a word
framer and can help the user synchronize the serial data
output, S
OUT
(Pins 11 and 12), in their applications.
Furthermore, PCLK can be used as a trigger for input
parallel data (Figure 14).
An internally generated voltage supply, the V
BB
pin, is
available to this device only. For single–ended input
conditions, the unused differential input is connected to V
BB
as a switching reference voltage. V
BB
may also rebias AC
coupled inputs. When used, decouple V
BB
and V
CC
via a
0.01 F capacitor and limit current sourcing or sinking to
0.5 mA. When not used, V
BB
should be left open. Also, both
outputs of the differential pair must be terminated (50 to
V
TT
) even if only one output is used.
Figure 14. PCLK as Trigger Application
TRIGGER
Pattern Generator
Data Format Logic
(FPGA, ASIC)
P
D
CLK
PCLK
EP446
P
D
SYNC
S
OUT
SERIAL DATA
CLK
RESET
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC100EP446FAR2G | 3.3 V/5 V 8-Bit CMOS/ECL/TTL Data Input Parallel/Serial Converter |
| MC100EP52DG | 3.3V / 5V ECL Differential Data and Clock D Flip−Flop |
| MC100EP52DR2G | 3.3V / 5V ECL Differential Data and Clock D Flip−Flop |
| MC100EP52DTG | 3.3V / 5V ECL Differential Data and Clock D Flip−Flop |
| MC100EP52DTR2G | 3.3V / 5V ECL Differential Data and Clock D Flip−Flop |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100EP446FAG | 制造商:ON Semiconductor 功能描述:Translator / Logic Level Converter IC |
| MC100EP446FAR2 | 功能描述:串行到并行邏輯轉(zhuǎn)換器 3.3V/5V ECL 8-Bit RoHS:否 制造商:Supertex 工作電源電壓: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-32 封裝:Tray |
| MC100EP446FAR2G | 功能描述:串行到并行邏輯轉(zhuǎn)換器 3.3V/5V ECL 8-Bit Serial to Parallel RoHS:否 制造商:Supertex 工作電源電壓: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-32 封裝:Tray |
| MC100EP446MNG | 功能描述:串行到并行邏輯轉(zhuǎn)換器 ECL PARA T/SERIAL RoHS:否 制造商:Supertex 工作電源電壓: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-32 封裝:Tray |
| MC100EP446MNR4G | 功能描述:串行到并行邏輯轉(zhuǎn)換器 ECL PARA T/SERIAL RoHS:否 制造商:Supertex 工作電源電壓: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-32 封裝:Tray |
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