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參數(shù)資料
| 型號(hào)： | MC100EP446FAG |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | 3.3 V/5 V 8-Bit CMOS/ECL/TTL Data Input Parallel/Serial Converter |
| 中文描述： | 100E SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, PQFP32 |
| 封裝： | LEAD FREE, PLASTIC, LQFP-32 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 278K |
| 代理商： | MC100EP446FAG |
MC10EP446, MC100EP446
http://onsemi.com
12
APPLICATION INFORMATION
The MC10/100EP446 is an integrated 8:1 parallel to serial
converter. An attribute for EP446 is that the parallel inputs
D0–D7 (Pins 17 – 24) can be configured to accept either
CMOS, ECL, or TTL level signals by a combination of
interconnects between V
EF
(Pin 27) and V
CF
(Pin 26) pins.
For CMOS input levels, leave V
EF
and V
CF
open. For ECL
operation, short V
CF
and V
EF
(Pins 26 and 27). For TTL
operation, connect a 1.5 V supply reference to V
CF
and leave
the V
EF
pin open. The 1.5 V reference voltage to V
CF
pin can
be accomplished by placing a 1.5 k or 500 between V
CF
and V
EE
for 3.3 V or 5.0 V power supplies, respectively.
Note: all pins requiring ECL voltage inputs must have a
50
terminating resistor to V
TT
(V
TT
= V
CC
– 2.0 V).
The CKSEL input (Pin 2) is provided to enable the user to
select the serial data rate output between internal clock data
rate or twice the internal clock data rate. For CKSEL LOW
operation, the time from when the parallel data is latched
to when the data is seen on the S
OUT
is on the falling edge
of the 7
th
clock cycle plus internal propagation delay
(Figure 7). Note the PCLK switches on the falling edge of
CLK.
Figure 7. Timing Diagram 1:8 Parallel to Serial Conversion with CKSEL LOW
CLK
SOUT
PCLK
D0
D0
2
D1
D2
D3
D4
D5
D6
D7
D2
2
D3
2
D4
2
D5
2
D6
2
D7
2
D0
3
D1
3
D2
3
D3
3
D4
3
D5
3
D6
3
D7
3
D1
2
CKSEL
D
1
D
1
D
1
D
1
D
1
D
1
D
1
D
1
D
2
D
2
D
2
D
2
D
2
D0
1
D2
1
D3
1
D4
1
D5
1
D6
1
D7
1
D1
1
D
2
D0
4
D1
4
D2
4
D3
4
D4
4
D5
4
D6
4
D7
4
1
2
3
4
5
6
7
Number of Clock Cycles from Data Latch to SOUT
Data Latched
Data Latched
Data Latched
Data Latched
D
2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC100EP446FAR2G | 3.3 V/5 V 8-Bit CMOS/ECL/TTL Data Input Parallel/Serial Converter |
| MC100EP52DG | 3.3V / 5V ECL Differential Data and Clock D Flip−Flop |
| MC100EP52DR2G | 3.3V / 5V ECL Differential Data and Clock D Flip−Flop |
| MC100EP52DTG | 3.3V / 5V ECL Differential Data and Clock D Flip−Flop |
| MC100EP52DTR2G | 3.3V / 5V ECL Differential Data and Clock D Flip−Flop |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100EP446FAG | 制造商:ON Semiconductor 功能描述:Translator / Logic Level Converter IC |
| MC100EP446FAR2 | 功能描述:串行到并行邏輯轉(zhuǎn)換器 3.3V/5V ECL 8-Bit RoHS:否 制造商:Supertex 工作電源電壓: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-32 封裝:Tray |
| MC100EP446FAR2G | 功能描述:串行到并行邏輯轉(zhuǎn)換器 3.3V/5V ECL 8-Bit Serial to Parallel RoHS:否 制造商:Supertex 工作電源電壓: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-32 封裝:Tray |
| MC100EP446MNG | 功能描述:串行到并行邏輯轉(zhuǎn)換器 ECL PARA T/SERIAL RoHS:否 制造商:Supertex 工作電源電壓: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-32 封裝:Tray |
| MC100EP446MNR4G | 功能描述:串行到并行邏輯轉(zhuǎn)換器 ECL PARA T/SERIAL RoHS:否 制造商:Supertex 工作電源電壓: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-32 封裝:Tray |
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