參數(shù)資料
型號(hào): MC100EP016AFAR2
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: 3.3 V ECL 8-Bit Synchronous Binary Up Counter
中文描述: 100E SERIES, SYN POSITIVE EDGE TRIGGERED 8-BIT UP BINARY COUNTER, PQFP32
封裝: LQFP-32
文件頁數(shù): 9/12頁
文件大?。?/td> 98K
代理商: MC100EP016AFAR2
MC100EP016A
http://onsemi.com
9
Applications Information
(continued)
EP01
Q0 to Q7
P0 to P7
CLK
TC
PE
CE
Figure 6. 32-Bit Cascaded EP016A Programmable Divider
LO
CLK
CLK
CLK
MSB
LSB
EP016
EP01
EP01
Q0 to Q7
Q0 to Q7
Q0 to Q7
P0 to P7
P0 to P7
P0 to P7
EP016
EP016
EP016
CLK
TC
PE
CE
CLK
CLK
TC
PE
CE
CLK
CLK
TC
PE
CE
CLK
Figure 6 shows a typical block diagram of a 32-bit divider
chain. Once again to maximize the frequency of operation
EP01 OR gates were used. For lower frequency applications
a slower OR gate could replace the EP01. Note that for a
16-bit divider the OR function feeding the PE (program
enable) input CANNOT be replaced by a wire OR tie as the
TC output of the least significant EP016A must also feed the
CE input of the most significant EP016A. If the two TC
outputs were OR tied the cascaded count operation would
not operate properly. Because in the cascaded form the PE
feedback is external and requires external gating, the
maximum frequency of operation will be significantly less
than the same operation in a single device.
Maximizing EP016A Count Frequency
The EP016A device produces 9 fast transitioning single
ended outputs, thus V
CC
noise can become significant in
situations where all of the outputs switch simultaneously in
the same direction. This V
CC
noise can negatively impact
the maximum frequency of operation of the device. Since
the device does not need to have the Q outputs terminated to
count properly, it is recommended that if the outputs are not
going to be used in the rest of the system they should be left
unterminated. In addition, if only a subset of the Q outputs
are used in the system only those outputs should be
terminated. Not terminating the unused outputs will not only
cut down the V
CC
noise generated but will also save in total
system power dissipation. Following these guidelines will
allow designers to either be more aggressive in their designs
or provide them with an extra margin to the published data
book specifications.
相關(guān)PDF資料
PDF描述
MC100EP40DTG 3.3V / 5V ECL Differential Phase−Frequency Detector
MC100EP40DTR2G 3.3V / 5V ECL Differential Phase−Frequency Detector
MC100EP91DWR2 2.5 V/3.3 V Any Level Positive Input to -3.3 V/-5.5 V NECL Output Translator
MC100EP91DWR2G 2.5 V/3.3 V Any Level Positive Input to -3.3 V/-5.5 V NECL Output Translator
MC100EP91MN 2.5 V/3.3 V Any Level Positive Input to -3.3 V/-5.5 V NECL Output Translator
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC100EP016AFAR2G 功能描述:計(jì)數(shù)器 IC 3.3V/5V ECL 8-Bit Up Counter RoHS:否 制造商:NXP Semiconductors 計(jì)數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計(jì)數(shù)法: 計(jì)數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel
MC100EP016AMNG 功能描述:計(jì)數(shù)器移位寄存器 3.3V ECL 8BT COUNTER BBG ECL RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel
MC100EP016AMNR4G 功能描述:計(jì)數(shù)器移位寄存器 3.3V ECL 8BT COUNTER BBG ECL RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel
MC100EP016FA 功能描述:IC COUNTER 8BIT SYNC ECL 32LQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 -計(jì)數(shù)器,除法器 系列:100EP 產(chǎn)品變化通告:1Q2012 Discontinuation 30/Mar/2012 標(biāo)準(zhǔn)包裝:2,500 系列:74HC 邏輯類型:二進(jìn)制計(jì)數(shù)器 方向:上 元件數(shù):1 每個(gè)元件的位元數(shù):12 復(fù)位:異步 計(jì)時(shí):- 計(jì)數(shù)速率:50MHz 觸發(fā)器類型:負(fù)邊沿 電源電壓:2 V ~ 6 V 工作溫度:-55°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP(0.173",4.40mm 寬) 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
MC100EP016FAG 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:3.3V / 5V ECL 8−Bit Synchronous Binary Up Counter