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參數(shù)資料
| 型號： | MC-9400A |
| 廠商： | NEC Corp. |
| 英文描述： | 320 (240)-BIT AC- PDP DRIVER MODULE |
| 中文描述： | 320（240）位交流等離子體平板顯示驅(qū)動模塊 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 82K |
| 代理商： | MC-9400A |
4
MC-9400A
PIN FUNCTIONS
Pin Symbol
Pin Name
Pin No.
I/O
Description
/PC
Polarity inverted
input
27
CN3
/PC = L : Polarity of all outputs inverted
BLK
Blanking input
25
CN3
BLK = H : All outputs = H or L
LE
Latch enable input
31
CN3
Automatically latches by a high level input at the rising edge of the
clock
A
11
to A
14
,
A
21
to A
24
,
A
31
to A
34
,
A
41
to A
44
,
A
51
to A
54
RIGHT data input
1 to 4
9 to 12
17 to 20
35 to 38
46
CN3
B
11
to B
14
,
B
21
to B
24
,
B
31
to B
34
,
B
41
to B
44
,
B
51
to B
54
LEFT data input
5 to 8
13 to 16
21 to 24
39 to 42
47 to 50
CN3
When R,/L = H
A
11
to A
14
, A
21
to A
24
, A
31
to A
34
, A
41
to A
44
, A
51
to A
54
: Input
B
11
to B
14
, B
21
to B
24
, B
31
to B
34
, B
41
to B
44
, B
51
to B
54
: Output
When R,/L = L
A
11
to A
14
, A
21
to A
24
, A
31
to A
34
, A
41
to A
44
, A
51
to A
54
: Output
B
11
to B
14
, B
21
to B
24
, B
31
to B
34
, B
41
to B
44
, B
51
to B
54
: Input
/CLK
Clock input
33
CN3
Executes a shift at the rising edge
R,/L
Shift control input
29
CN3
Right shift mode by H
SR
1
: A
1
→
S
1
... S
61
→
B
1
(SR
2
, SR
3
, and SR
4
also same direction)
Left shift mode by L
SR
1
: B
1
→
S
61
... S
1
→
A
1
(SR
2
, SR
3
, and SR
4
also same direction)
O
1
to O
320
High breakdown
voltage output
1 to 320
FPC
150 V, 40mA (MAX.)
V
DD1
Logic block power
supply
1
CN1
CN2
5 V ± 10 %
V
DD2
Driver block power
supply
3
CN1
CN2
30 V to 130 V
2
CN1
CN2
GND
Ground
26,28,
30,32,
34
CN3
Connected to system ground
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