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參數(shù)資料
| 型號： | MC-428LFH641 |
| 廠商： | NEC Corp. |
| 英文描述： | 3.3 V Operation 8M-Word By 72-Bit Dynamic RAM Module(工作電壓為3.3V的DRAM模塊) |
| 中文描述： | 3.3 V工作電壓800萬字由72位動(dòng)態(tài)內(nèi)存模塊（工作電壓為3.3伏的內(nèi)存模塊） |
| 文件頁數(shù)： | 10/32頁 |
| 文件大小： | 273K |
| 代理商： | MC-428LFH641 |
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10
MC-428LFH641
Write Cycle
Parameter
Symbol
t
RAC
= 50 ns
t
RAC
= 60 ns
Unit
Notes
MIN.
MAX.
MIN.
MAX.
/WE hold time referenced to /CAS
t
WCH
7
10
ns
1
/WE pulse width
t
WP
7
10
ns
1
/WE lead time referenced to /RAS
t
RWL
13
15
ns
/WE lead time referenced to /CAS
t
CWL
7
10
ns
/WE setup time
t
WCS
0
0
ns
2
/OE hold time
t
OEH
0
0
ns
Data-in setup time
t
DS
0
0
ns
3
Data-in hold time
t
DH
7
10
ns
3
Notes 1.
t
WP
(MIN.)
is applied to late write cycles or read modify write cycles. In early write cycles, t
WCH
(MIN.)
should be met.
2.
If t
WCS
≥
t
WCS
(MIN.)
, the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
3.
t
DS
(MIN.)
and t
DH
(MIN.)
are referenced to the /CAS falling edge in early write cycles. In late write cycles and
read modify write cycles, they are referenced to the /WE falling edge.
Read Modify Write Cycle
Parameter
Symbol
t
RAC
= 50 ns
t
RAC
= 60 ns
Unit
Note
MIN.
MAX.
MIN.
MAX.
Read modify write cycle time
t
RWC
107
133
ns
/RAS to /WE delay time
t
RWD
64
77
ns
1
/CAS to /WE delay time
t
CWD
27
32
ns
1
Column address to /WE delay time
t
AWD
39
47
ns
1
Note
1.
If t
WCS
≥
t
WCS (MIN.)
, the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If t
RWD
≥
t
RWD
(MIN.)
, t
CWD
≥
t
CWD
(MIN.)
, t
AWD
≥
t
AWD
(MIN.)
and t
CPWD
≥
t
CPWD (MIN.)
, the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.
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