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參數(shù)資料
| 型號(hào)： | MBR0520LTI |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | DB-LM3S102 Daughterboard |
| 中文描述： | 同步降壓控制器，帶有預(yù)偏置啟動(dòng)和可選時(shí)鐘同步 |
| 文件頁(yè)數(shù)： | 4/23頁(yè) |
| 文件大?。?/td> | 1002K |
| 代理商： | MBR0520LTI |
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Electrical Characteristics
(Continued)
V
= 3.3V unless otherwise indicated. Typicals and limits appearing in plain type apply for T
= T
= 25C. Limits appearing in
boldface type apply over full Operating Temperature Range. Datasheet min/max specification limits are guaranteed by design,
test, or statistical analysis.
Symbol
GATE DRIVE
I
Q-BOOT
R
HG_UP
Parameter
Conditions
Min
Typ
Max
Units
BOOT Pin Quiescent Current
High-Side MOSFET Driver
Pull-Up ON resistance
High-Side MOSFET Driver
Pull-Down ON resistance
Low-Side MOSFET Driver Pull-Up
ON resistance
Low-Side MOSFET Driver
Pull-Down ON resistance
V
BOOT
= 12V, V
SD
= 0
18
90
μA
V
BOOT
= 5V
@
350 mA Sourcing
2.7
R
HG_DN
350 mA Sinking
0.8
R
LG_UP
V
BOOT
= 5V
@
350 mA Sourcing
2.7
R
LG_DN
350 mA Sinking
0.8
OSCILLATOR
f
SW
PWM Frequency
R
FADJ
= 750 k
R
FADJ
= 100 k
R
FADJ
= 42.2 k
R
FADJ
= 18.7 k
50
300
600
1000
kHz
475
725
External Synchronizing Signal
Frequency
Synchronization Signal Low
Threshold
Synchronization Signal High
Threshold
Max High-Side Duty Cycle
Voltage Swing = 0V to V
CC
250
1000
SYNC
L
f
SW
= 250 kHz to 1 MHz
1
V
SYNC
H
f
SW
= 250 kHz to 1 MHz
2
V
D
MAX
f
SW
= 300 kHz
f
SW
= 600 kHz
f
SW
= 1 MHz
86
78
67
%
LOGIC INPUTS AND OUTPUTS
V
STBY-IH
Standby High Trip Point
V
FB
= 0.575V, V
BOOT
= 3.3V
V
SD
Rising
V
FB
= 0.575V, V
BOOT
= 3.3V
V
SD
Falling
V
SD
Rising
V
SD
Falling
V
FB
Falling
V
FB
Rising
V
FB
Falling
V
FB
Rising
1.1
V
V
STBY-IL
Standby Low Trip Point
0.232
V
V
SD-IH
V
SD-IL
SD Pin Logic High Trip Point
SD Pin Logic Low Trip Point
PWGD Pin Trip Points
PWGD Pin Trip Points
PWGD Hysteresis
1.3
V
V
V
V
0.8
0.408
0.677
V
PWGD-TH-LO
V
PWGD-TH-HI
V
PWGD-HYS
0.434
0.710
60
90
0.457
0.742
mV
Note 1:
Absolute maximum ratings indicate limits beyond which damage to the device may occur.
Operating ratings
indicate conditions for which the device
operates correctly.
Operating Ratings
do not imply guaranteed performance limits.
Note 2:
The power MOSFETs can run on a separate 1V to 14V rail (Input voltage, V
IN
). Practical lower limit of V
IN
depends on selection of the external MOSFET.
See the MOSFET GATE DRIVERS section under Application Information for further details.
Note 3:
ESD using the human body model which is a 100pF capacitor discharged through a 1.5 k
resistor into each pin.
L
www.national.com
4
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