參數(shù)資料
型號: MBM30LV0064-PFTN
廠商: FUJITSU LTD
元件分類: DRAM
英文描述: 64M (8M X 8) BIT NAND-type
中文描述: 8M X 8 FLASH 3.3V PROM, 7000 ns, PDSO40
封裝: 0.80 MM PITCH, PLASTIC, TSOP2-44/40
文件頁數(shù): 33/43頁
文件大?。?/td> 397K
代理商: MBM30LV0064-PFTN
MBM30LV0064
33
(9) Address input in 4 cycles
The device will get addresses in three cycles. If addresses are input in four cycles, address input in the fourth
cycle will be ignored in the chip.
Internal read operation starts when WE in the third cycle goes high.
Read operation
ignored
CLE
CE
WE
ALE
I/O0 to I/O7
R/B
00h, 01h or 50h
Address input
Figure 30 Read Operation when 4 Address Cycles are Input
Program operation
CLE
CE
WE
ALE
I/O0 to I/O7
80h
Address input
ignored
Data input
Figure 31 Program Operation when 4 Address Cycles are Input
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