參數(shù)資料
型號(hào): MBM30LV0064-PFTN
廠商: FUJITSU LTD
元件分類: DRAM
英文描述: 64M (8M X 8) BIT NAND-type
中文描述: 8M X 8 FLASH 3.3V PROM, 7000 ns, PDSO40
封裝: 0.80 MM PITCH, PLASTIC, TSOP2-44/40
文件頁(yè)數(shù): 17/43頁(yè)
文件大?。?/td> 397K
代理商: MBM30LV0064-PFTN
MBM30LV0064
17
(Continued)
Notes: 1. AC Test Conditions:
2. The time to go from CE high to Ready depends on the pull-up resister of the R/B pin (see Application
Notes (6)) toward the end of this document.
3. In case that toggling CE to high after access to the last address (address 527) in the resister in the read
mode (1), (2), and (3), the CE high time must be held for 100 ns or more when the delay time of CE with
respect to RE is 0 to 200 ns (see the figure below). When the CE delay time is within 30 ns, the device
is kept in the Ready state and will output no Busy signal.
Parameter
Symbol
Value
Unit
Min.
Max.
ALE Low to RE Low (Read Cycle)
t
AR2
50
ns
RE Last Clock Rising Edge to Busy (in Sequential Read)
t
RB
100
ns
CE High to Ready (in Case of Interception by CE in Read Mode)
(Note 2)
t
CRY
50 + tr
(R/B)
ns
Device Resetting Time (Read/Program/Erase)
t
RST
5/10/500
μ
s
Operating range
V
CC
= 2.7 to 3.6 V
V
CC
= 3.0 to 3.6 V
Input level
2.4 V/0.4 V
Input comparison level
1.5 V/1.5 V
Output data comparison level
1.5 V/1.5 V
Output load
1TTL
Load capacitance (C
L
)
50 pF
100 pF
Transition time (t
T
)
5 ns
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