MBM29PL12LM
10
36
DQ
5
Exceeded Timing Limits
DQ
5
will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
these conditions DQ
5
will produce a “1”. This is a failure condition indicating that the program or erase cycle was
not successfully completed. Data Polling is the only operating function of the device under this condition. The
CE circuit will partially power down the device under these conditions (to approximately 2 mA). The OE and WE
pins will control the output disable functions as described in “MBM29PL12LM User Bus Operations (Word
Mode : BYTE = V
IH
)” and “MBM29PL12LM User Bus Operations (Byte Mode : BYTE = V
IL
)” in
■
DEVICE BUS
OPERATION.
The DQ
5
failure condition may also appear if a user tries to program a non blank location without pre-erase. In
this case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ
7
bit and DQ
6
never stop toggling. Once the device has exceeded timing limits, the DQ
5
bit will indicate a “1”. Note that this is not a device failure condition since the device was incorrectly used. If this
occurs, reset the device with command sequence.
DQ
3
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ
3
will
remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates a valid erase command has been written, DQ
3
may be used to
determine whether the sector erase timer window is still open. If DQ
3
is “1” the internally controlled erase cycle
has begun. If DQ
3
is “0”, the device will accept additional sector erase commands. To insure the command has
been accepted, the system software should check the status of DQ
3
prior to and following each subsequent
Sector Erase command. If DQ
3
were high on the second status check, the command may not have been accepted.
See “Hardware Sequence Flags”.
DQ
2
Toggle Bit II
This Toggle bit II, along with DQ
6
, can be used to determine whether the devices are in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ
2
to toggle during the Embedded Erase Algorithm. If the
devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ
2
to toggle. When the device is in the erase-suspended-program mode, successive reads from the non-erase
suspended sector will indicate a logic “1” at the DQ
2
bit.
DQ
6
is different from DQ
2
in that DQ
6
toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these two status bits, along with that of DQ
7
, is summarized
as follows:
For example, DQ
2
and DQ
6
can be used together to determine if the erase-suspend-read mode is in progress.
(DQ
2
toggles while DQ
6
does not.) See also “Hardware Sequence Flags” and “DQ
2
vs. DQ
6
” in
■
TIMING DIA-
GRAM.
Furthermore, DQ
2
can also be used to determine which sector is being erased. At the erase mode, DQ
2
toggles
if this bit is read from an erasing sector.