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參數(shù)資料
| 型號： | MBM29PL12LM10PCN |
| 廠商： | FUJITSU LTD |
| 元件分類： | DRAM |
| 英文描述： | FLASH MEMORY 128 M (16M ?8/8M ?16) BIT |
| 中文描述： | 8M X 16 FLASH 3V PROM, 100 ns, PDSO56 |
| 封裝： | PLASTIC, TSOP1-56 |
| 文件頁數(shù)： | 29/72頁 |
| 文件大?。?/td> | 1036K |
| 代理商： | MBM29PL12LM10PCN |
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MBM29PL12LM
10
29
Programming is allowed in any address sequence and across sector boundaries. Beware that a data “0” cannot
be programmed back to a “1”. Attempting to do so may result in either failure condition or an apparent success
according to the data polling algorithm. But a read from reset command will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.
Note that attempting to program a “1” over a “0” will result in programming failure. This precaution is the same
with Fujitsu standard NOR devices. “Embedded Program
TM
Algorithm” in
■
FLOW CHART illustrates the Em-
bedded Program
TM
Algorithm using typical command strings and bus operations.
Program Suspend/Resume
The Program Suspend command allows the system to interrupt a program operation so that data can be read
from any address. Writing the Program Suspend command (B0h) during Embedded Program operation imme-
diately suspends the programming. Refer to "Erase Suspend/Resume" for the detail.
When the Program Suspend command is written during a programming process, the chip halts the program
operation within 1
μ
s and suspend the status bits.After the program operation has been suspended, the system
can read data from any address. Normal read timing and command definitions apply. The data at program-
suspended address is not valid.
After the Program Resume command (30h) is written, the chip reverts to programming. The system can determine
the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation.
See "Write Operation Status" for more information.
When issuing program suspend command in 4
μ
s after issuing program command, determine the status of
program operation by reading status bit at more 4
μ
s after issuing program resume command.
The system also writes the Autoselect command sequence in the Program Suspend mode. The device allows
reading Autoselect codes at the addresses within programming sectors, since the codes are not stored in the
memory. When the device exits the Autoselect mode, the device reverts to the Program Suspend mode, and is
ready for another valid operation. See "Autoselect Command Sequence" for more information.
The system must write the Program Resume command to exit from the Program Suspend mode and continue
the programming operation. Further writes of the Resume command are ignored. Another Program Suspend
command can be written after the chip resumes programming.
Write Buffer Programming Operations
Write Buffer Programming allows the system write to series of 16 words in one programming operation. This
results in faster effective word programming time than the standard programming algorithms. The Write Buffer
Programming command sequence is initialized by first writing two unlock cycles. This is followed by a third write
cycle selecting the Sector Address in which programming will occur. In forth cycle contains both Sector Address
and unique code for data bus width will be loaded into the page buffer at the Sector Address in which programming
will occur.
The system then writes the starting address/data combination. This “starting address” must be the same Sector
Address used in third and fourth cycles and its lower addresses of A
3
to A
0
should be 0h. All subsequent address
must be incremented by 000Fh. Addresses are latched on the falling edge of CE or WE, whichever happens
later and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of the
last CE or WE (whichever happens first) starts programming. Upon executing the Write Buffer Programming
Operations command sequence, the system is not required to provide further controls. The device will automat-
ically provide adequate internally generated program pulses and verify the programmed cell margin.
DQ
7
(Data Polling), DQ
6
(Toggle Bit), DQ
5
(Exceeded Timing Limits), DQ
1
(Write-to-Buffer Abort) should be mon-
itored to determine the device status during Write Buffer Programming. In addition to these functions, it is also
possible to indicate to the host system that Write Buffer Programming Operations are either in progress or have
been completed by RY/BY. See “Hardware Sequence Flags”.
The Data polling techniques described in “Data Polling Algorithm” in
■
FLOW CHART should be used while
monitoring the last address location loaded into the write buffer. In addition, it is not neccessary to specify an
address in Toggle Bit techniques described in “Toggle Bit Algorithm” in
■
FLOW CHART. The automatic pro-
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