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參數(shù)資料
| 型號： | MB9AF312LPMC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP64 |
| 封裝： | 0.65 MM PITCH, PLASTIC, LQFP-64 |
| 文件頁數(shù)： | 74/114頁 |
| 文件大?。?/td> | 1357K |
| 代理商： | MB9AF312LPMC |
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ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
62
13.2.4 PCICR – Pin Change Interrupt Control Register
Bit 7:3 – Reserved
These bits are unused bits in the Atmel ATmega48PA/88PA/168PA, and will always read as zero.
Bit 2 – PCIE2: Pin Change Interrupt Enable 2
When the PCIE2 bit is set (one) and the I-bit in the status register (SREG) is set (one), pin change interrupt 2 is enabled. Any
change on any enabled PCINT[23:16] pin will cause an interrupt. The corresponding interrupt of Pin change interrupt request
is executed from the PCI2 interrupt vector. PCINT[23:16] pins are enabled individually by the PCMSK2 register.
Bit 1 – PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the status register (SREG) is set (one), pin change interrupt 1 is enabled. Any
change on any enabled PCINT[14:8] pin will cause an interrupt. The corresponding interrupt of pin change interrupt request
is executed from the PCI1 interrupt vector. PCINT[14:8] pins are enabled individually by the PCMSK1 register.
Bit 0 – PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the status register (SREG) is set (one), pin change interrupt 0 is enabled. Any
change on any enabled PCINT[7:0] pin will cause an interrupt. The corresponding interrupt of pin change interrupt request is
executed from the PCI0 interrupt vector. PCINT[7:0] pins are enabled individually by the PCMSK0 register.
13.2.5 PCIFR – Pin Change Interrupt Flag Register
Bit 7:3 – Reserved
These bits are unused bits in the Atmel ATmega48PA/88PA/168PA, and will always read as zero.
Bit 2 – PCIF2: Pin Change Interrupt Flag 2
When a logic change on any PCINT[23:16] pin triggers an interrupt request, PCIF2 becomes set (one). If the I-bit in SREG
and the PCIE2 bit in PCICR are set (one), the MCU will jump to the corresponding interrupt vector. The flag is cleared when
the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
Bit 1 – PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT[14:8] pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG
and the PCIE1 bit in PCICR are set (one), the MCU will jump to the corresponding interrupt vector. The flag is cleared when
the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
Bit 0 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT[7:0] pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and
the PCIE0 bit in PCICR are set (one), the MCU will jump to the corresponding interrupt vector. The flag is cleared when the
interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
Bit
76543210
–––––
PCIE2
PCIE1
PCIE0
PCICR
Read/Write
RRRRR
R/W
Initial Value
00000000
Bit
76543210
–––––
PCIF2
PCIF1
PCIF0
PCIFR
Read/Write
RRRRR
R/W
Initial Value
00000000
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