參數(shù)資料
型號(hào)： MB9AF312LPMC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP64
封裝： 0.65 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù)： 55/114頁
文件大?。?/td> 1357K
代理商： MB9AF312LPMC
45
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
11.8
Watchdog Timer
11.8.1 Features
●
Clocked from separate on-chip oscillator
●
3 Operating modes
●
Interrupt
●
System reset
●
Interrupt and system reset
●
Selectable time-out period from 16ms to 8s
●
Possible hardware fuse watchdog always on (WDTON) for fail-safe mode
11.8.2 Overview
The Atmel ATmega48PA/88PA/168PA has an enhanced watchdog timer (WDT). The WDT is a timer counting cycles of a
separate on-chip 128kHz oscillator. The WDT gives an interrupt or a system reset when the counter reaches a given time-
out value. In normal operation mode, it is required that the system uses the WDR - watchdog timer reset - instruction to
restart the counter before the time-out value is reached. If the system doesn't restart the counter, an interrupt or system reset
will be issued.
Figure 11-7. Watchdog Timer
In interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used to wake the device from
sleep-modes, and also as a general system timer. One example is to limit the maximum time allowed for certain operations,
giving an interrupt when the operation has run longer than expected. In system reset mode, the WDT gives a reset when the
timer expires. This is typically used to prevent system hang-up in case of runaway code. The third mode, interrupt and
system reset mode, combines the other two modes by first giving an interrupt and then switch to system reset mode. This
mode will for instance allow a safe shutdown by saving critical parameters before a system reset.
The watchdog always on (WDTON) fuse, if programmed, will force the watchdog timer to system reset mode. With the fuse
programmed the system reset mode bit (WDE) and interrupt mode bit (WDIE) are locked to 1 and 0 respectively. To further
ensure program security, alterations to the watchdog set-up must follow timed sequences. The sequence for clearing WDE
and changing time-out configuration is as follows:
1.
In the same operation, write a logic one to the watchdog change enable bit (WDCE) and WDE. A logic one must
be written to WDE regardless of the previous value of the WDE bit.
2.
Within the next four clock cycles, write the WDE and watchdog prescaler bits (WDP) as desired, but with the
WDCE bit cleared. This must be done in one operation.
OSC/64K
OSC/16K
OSC/2K
OSC/4K
OSC/8K
OSC/32K
OSC/128K
OSC/256K
OSC/512K
OSC/1024K
Watchdog
Prescaler
WDP0
WDE
WATCHDOG
RESET
WDIF
WDIE
WDP1
WDP2
WDP3
MCU RESET
INTERRUPT
128kHz
Oscillator
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