32 Kbyte SRAM – Implemented as two " />
參數(shù)資料
型號： MB91F487PMC-GE1
廠商： Fujitsu Semiconductor America Inc
文件頁數(shù)： 67/94頁
文件大小： 0K
描述： IC MCU 512KB FLASH 100-LQFP
標(biāo)準(zhǔn)包裝： 1
系列： FR MB91480
核心處理器： FR60 RISC
芯體尺寸： 32-位
速度： 80MHz
連通性： I²C，F(xiàn)IFO，SIO
外圍設(shè)備： DMA，PWM，WDT
輸入/輸出數(shù)： 77
程序存儲器容量： 512KB（512K x 8）
程序存儲器類型： 閃存
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 14x8/10b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-LQFP
包裝： 托盤
其它名稱： 865-1096
71
32015G–AVR32–09/09
AT32AP7001
9.
Memories
9.1
Embedded Memories
32 Kbyte SRAM
– Implemented as two 16Kbyte blocks
– Single cycle access at full bus speed
9.2
Physical Memory Map
The system bus is implemented as an HSB bus matrix. All system bus addresses are fixed, and
they are never remapped in any way, not even in boot. Note that AT32AP7001 by default uses
segment translation, as described in the AVR32 Architecture Manual. The 32 bit physical
address space is mapped as follows:
Accesses to unused areas returns an error result to the master requesting such an access.
The bus matrix has the several masters and slaves. Each master has its own bus and its own
decoder, thus allowing a different memory mapping per master. The master number in the table
below can be used to index the HMATRIX control registers. For example, MCFG2 is associated
with the HSB-HSB bridge.
Table 9-1.
AT32AP7001 Physical Memory Map
Start Address
Size
Device
0x0000_0000
64 Mbyte
EBI SRAM CS0
0x0400_0000
64 Mbyte
EBI SRAM CS4
0x0800_0000
64 Mbyte
EBI SRAM CS2
0x0C00_0000
64 Mbyte
EBI SRAM CS3
0x1000_0000
256 Mbyte
EBI SRAM/SDRAM CS1
0x2000_0000
64 Mbyte
EBI SRAM CS5
0x2400_0000
16 Kbyte
Internal SRAM 0
0x2400_4000
16 Kbyte
Internal SRAM1
0xFF20_0000
1 KByte
DMACA configuration
0xFF30_0000
1 MByte
USBA Data
0xFFE0_0000
1 MByte
PBA
0xFFF0_0000
1 MByte
PBB
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