參數(shù)資料
型號： MB91F487PMC-GE1
廠商： Fujitsu Semiconductor America Inc
文件頁數(shù)： 52/94頁
文件大?。?/td> 0K
描述： IC MCU 512KB FLASH 100-LQFP
標(biāo)準(zhǔn)包裝： 1
系列： FR MB91480
核心處理器： FR60 RISC
芯體尺寸： 32-位
速度： 80MHz
連通性： I²C，F(xiàn)IFO，SIO
外圍設(shè)備： DMA，PWM，WDT
輸入/輸出數(shù)： 77
程序存儲器容量： 512KB（512K x 8）
程序存儲器類型： 閃存
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 14x8/10b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-LQFP
包裝： 托盤
其它名稱： 865-1096
58
32015G–AVR32–09/09
AT32AP7001
PICOVMUL – PICO Vector Multiplication
Description
Performs three vector multiplications where the input pixels taken from the INPIXn registers depends on the Input Selection
Mode and the input pixel addresses given in the instruction. The results from the VMUs are then scaled and saturated to
unsigned 8-bit values before being inserted into the OUTPIXn registers. Which pixels to update in the OUTPIXn registers
depend upon the Output Insertion Mode and the output pixel address given in the instruction.
Operation:
I.
OFFSET_SCALE = COEFF_FRAC_BITS - OFFSET_FRAC_BITS
if ( Input Selection Mode == Horizontal Filter Mode ) then
else if ( Input Selection Mode == Vertical Filter Mode ) then
else if ( Input Selection Mode == Transformation Mode ) then
if ( Output Insertion Mode == Packed Insertion Mode ) then
OUT(d*3 + 0)
← SATSU(ASR(VMU0_OUT, COEFF_FRAC_BITS), 8);
OUT(d*3 + 1)
← SATSU(ASR(VMU1_OUT, COEFF_FRAC_BITS), 8);
OUT(d*3 + 2)
← SATSU(ASR(VMU2_OUT, COEFF_FRAC_BITS), 8);
else if ( Output Insertion Mode == Planar Insertion Mode ) then
OUT(d + 0)
← SATSU(ASR(VMU0_OUT, COEFF_FRAC_BITS), 8);
OUT(d + 4)
← SATSU(ASR(VMU1_OUT, COEFF_FRAC_BITS), 8);
OUT(d + 8)
← SATSU(ASR(VMU2_OUT, COEFF_FRAC_BITS), 8);
VMU0_OUT
COEFF0_0 COEFF0_1 COEFF0_2
IN(x+0)
IN(x+1)
IN(x+2)
OFFSET0 << OFFSET_SCALE
+
=
VMU1_OUT
COEFF1_0 COEFF1_1 COEFF1_2
IN(y+0)
IN(y+1)
IN(y+2)
OFFSET1 << OFFSET_SCALE
+
=
VMU2_OUT
COEFF2_0 COEFF2_1 COEFF2_2
IN(z+0)
IN(z+1)
IN(z+2)
OFFSET2 << OFFSET_SCALE
+
=
VMU0_OUT
COEFF0_0 COEFF0_1 COEFF0_2
IN((x+0)%11)
IN((x+4)%11)
IN((x+8)%11)
OFFSET0 << OFFSET_SCALE
+
=
VMU1_OUT
COEFF1_0 COEFF1_1 COEFF1_2
IN((y+0)%11)
IN((y+4)%11)
IN((y+8)%11)
OFFSET1 << OFFSET_SCALE
+
=
VMU2_OUT
COEFF2_0 COEFF2_1 COEFF2_2
IN((z+0)%11)
IN((z+4)%11)
IN((z+8)%11)
OFFSET2 << OFFSET_SCALE
+
=
VMU0_OUT
VMU1_OUT
VMU2_OUT
COEFF0_0 COEFF0_1 COEFF0_2
COEFF1_0 COEFF1_1 COEFF1_2
COEFF2_0 COEFF2_1 COEFF2_2
INx
INy
INz
OFFSET0 << OFFSET_SCALE
OFFSET1 << OFFSET_SCALE
OFFSE20 << OFFSET_SCALE
+
=
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