參數(shù)資料
型號(hào)： MB91F487PMC-GE1
廠商： Fujitsu Semiconductor America Inc
文件頁(yè)數(shù)： 1/94頁(yè)
文件大?。?/td> 0K
描述： IC MCU 512KB FLASH 100-LQFP
標(biāo)準(zhǔn)包裝： 1
系列： FR MB91480
核心處理器： FR60 RISC
芯體尺寸： 32-位
速度： 80MHz
連通性： I²C，F(xiàn)IFO，SIO
外圍設(shè)備： DMA，PWM，WDT
輸入/輸出數(shù)： 77
程序存儲(chǔ)器容量： 512KB（512K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 14x8/10b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-LQFP
包裝： 托盤
其它名稱： 865-1096
DS07-16901-4E
a
FUJITSU MICROELECTRONICS
DATA SHEET
Copyright2006-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2008.3
“Check Sheet” is seen at the following support page
URL:http://edevice.fujitsu.com/micom/en-support/
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Be sure to refer to the “Check Sheet” for the latest cautions on development.
32-bit Microcontrollers
CMOS
FR60 MB91470/480 Series
MB91482/F475/F478/F479/F482/F487/
MB91FV470
■ DESCRIPTION
The MB91470/480 series is Fujitsu's general-purpose 32-bit RISC microcontroller, which is designed for
embedded control applications that require high-speed processing performance.
This series uses the FR60 CPU, which is compatible with the FR* family of CPUs.
* : FR is a line of products of FUJITSU MICROELECTRONICS Limited.
■ FEATURES
FR60 CPU
32-bit RISC, load/store architecture, five-stage pipeline
Operating frequency of 80 MHz (PLL clock multiplied)
16-bit fixed-length instructions (basic instructions)
Instruction execution speed : one instruction per cycle
Memory-to-memory transfer, bit processing, barrel shift instructions, etc. :
instructions suitable for embedded applications
Function entry and exit instructions, multi load/store instructions of register contents :
instructions compatible with C language.
Register interlock function to facilitate assembly-language coding
Built-in multiplier/instruction-level support
Signed 32-bit multiplication : 5 cycles
Signed 16-bit multiplication : 3 cycles
Interrupts (save PC and PS) : 6 cycles, 16 priority levels
Harvard architecture allowing program access and data access to be executed simultaneously
Instructions compatible with the FR family
(Continued)
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