參數(shù)資料
型號: MB91F467SAPMC-GSE2
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP176
封裝: 24 X 24 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, PLASTIC, LQFP-176
文件頁數(shù): 89/144頁
文件大?。?/td> 5502K
代理商: MB91F467SAPMC-GSE2
MB91460S Series
DS07-16617-3E
49
2.1.7.
Event Control
EVCTRL: Address 072F0h
Bit31
reserved Bit
Always write 0 to this bit. The read value is the value written.
FRST
0(def)
FIFO in normal operation
1
FIFO pointers are reset pulse (set to 0 after 1 cycle)
MODE
0 (def)
level mode On full FIFO new Events are discarded
1
ring mode
LVIEN
0(def)
Level Interrupt disabled
1
Level Interrupt enabled
LVIRQ
0(def)
Level Interrupt not active
1
Level Interrupt active (if STATUS>=LEVEL)
*Remark: On a RMW instruction a “1” is read; write “0” clears the interrupt; write “1” is ignored
OFLIEN
0(def)
Event Buffer Overflow Interrupt disabled
1
Event Buffer Overflow Interrupt enabled
OFLIRQ
0(def)
Event Buffer Overflow Interrupt not active
1
Event Buffer Overflow Interrupt active
*Remark: On a RMW instruction a “1” is read; write “0” clears the interrupt; write “1” is ignored
EVIEN
0(def)
Event Buffer Interrupt disabled
1
Event Buffer Interrupt enabled
EVIRQ
0(def)
Event Buffer Interrupt not active
1
Event Buffer Interrupt active
*Remark: On a RMW instruction a “1” is read; write “0” clears the interrupt; write “1” is ignored
Set by hardware, reset by software
STATUS[7:0]
0-128
Current FIFO filling status read only
LEVEL[7:0]
0-128
FIFO interrupt level (128 default)
31
30
29
28
27
26
25
24
EVCTRL
reserved
------
FRST
R/W0
R0
R0/W
23
22
21
20
19
18
17
16
MODE
-
LVIEN
LVIRQ
OFLIEN
OFLIRQ
EVIEN
EVIRQ
R/W
R0
R/W
R(RM1)/W
R/W
R(RM1)/W
R/W
R(RM1)/W
15
14
13
12
11
10
9
8
RRRRRRRR
76543210
R/W
STATUS[7:0]
LEVEL[7:0]
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